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RISC-V: Remove -Wno-psabi for test build option [NFC]

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Just notice there are some test case still have -Wno-psabi option,
which is deprecated now.  Remove them all for riscv test cases.

The below test are passed for this patch.
* The riscv rvv regression test.

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/pr109244.C: Remove deprecated
	-Wno-psabi option.
	* g++.target/riscv/rvv/base/pr109535.C: Ditto.
	* gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
This commit is contained in:
Pan Li 2024-04-11 11:42:40 +08:00
parent e40a3d8651
commit f3fdcf4a37
62 changed files with 62 additions and 62 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
gcc/testsuite/g++.target/riscv/rvv/base/pr109244.C
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O2 -Wno-psabi" } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */
typedef int a;
using c = float;
template < typename > using e = int;

2
gcc/testsuite/g++.target/riscv/rvv/base/pr109535.C
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -Wno-psabi" } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
typedef long size_t;
typedef signed char int8_t;

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -mrvv-vector-bits=zvl" } */
#include "riscv_vector.h"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-1.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-2.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-3.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-4.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-5.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress-6.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-1.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
#include <assert.h>
#include "compress-1.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-2.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
#include <assert.h>
#include "compress-2.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-3.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
#include <assert.h>
#include "compress-3.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-4.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
#include <assert.h>
#include "compress-4.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-5.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
#include <assert.h>
#include "compress-5.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/compress_run-6.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
#include <assert.h>
#include "compress-6.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-1.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive-2.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-1.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
#include <assert.h>
#include "consecutive-1.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/consecutive_run-2.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
#include <assert.h>
#include "consecutive-2.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-march=rv64gcv_zvfhmin -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
#include "merge-1.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
#include "merge-2.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
#include "merge-3.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
#include "merge-4.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
#include "merge-5.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
#include "merge-6.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl -Wno-psabi" } */
/* { dg-options "-O3 -mrvv-vector-bits=zvl" } */
#include "merge-7.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
#include "perm.h"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
#include "perm.h"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
#include "perm.h"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
#include "perm.h"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
#include "perm.h"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
#include "perm.h"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d" } */
#include "perm.h"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */
/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
#include "perm-1.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */
/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
#include "perm-2.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */
/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
#include "perm-3.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */
/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
#include "perm-4.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */
/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
#include "perm-5.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-mrvv-vector-bits=zvl -O3 -Wno-psabi" } */
/* { dg-options "-mrvv-vector-bits=zvl -O3" } */
#include "perm-6.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c
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@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-options "-mrvv-vector-bits=zvl -O0 -Wno-psabi" } */
/* { dg-options "-mrvv-vector-bits=zvl -O0" } */
#include "perm-7.c"

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1u.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
View File

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2u.c
View File

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
View File

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3u.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
View File

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4u.c
View File

@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv -mabi=lp64d -Wno-pedantic" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c
View File

@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */
/* { dg-additional-options "-std=c99 -Wno-pedantic" } */
#include <assert.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-runu.c
View File

@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */
/* { dg-additional-options "-std=c99 -Wno-pedantic" } */
#include <assert.h>
#include <limits.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c
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@ -1,5 +1,5 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic -Wno-psabi" } */
/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic" } */
#include <stdint-gcc.h>

2
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c
View File

@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */
/* { dg-additional-options "-std=c99 -Wno-pedantic" } */
#include <assert.h>