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git://gcc.gnu.org/git/gcc.git
synced 2025-02-28 11:45:52 +08:00
aarch64: Support conditional unpacked UXT on SVE
This patch extends the conditional UXT patterns from SVE_FULL_I to SVE_I. It doesn't matter in this case whether the type suffix is taken from the element size or the container size. gcc/ * config/aarch64/aarch64-sve.md (*cond_uxt<mode>_2): Extend from SVE_FULL_I to SVE_I. (*cond_uxt<mode>_any): Likewise. gcc/testsuite/ * gcc.target/aarch64/sve/cond_uxt_5.c: New test. * gcc.target/aarch64/sve/cond_uxt_5_run.c: Likewise. * gcc.target/aarch64/sve/cond_uxt_6.c: Likewise. * gcc.target/aarch64/sve/cond_uxt_6_run.c: Likewise. * gcc.target/aarch64/sve/cond_uxt_7.c: Likewise. * gcc.target/aarch64/sve/cond_uxt_7_run.c: Likewise. * gcc.target/aarch64/sve/cond_uxt_8.c: Likewise. * gcc.target/aarch64/sve/cond_uxt_8_run.c: Likewise.
This commit is contained in:
Richard Sandiford
parent
07fb24a3da
commit
f3c5d1fa53
@ -3135,12 +3135,12 @@
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;; The canonical form of this operation is an AND of a constant rather
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;; than (zero_extend (truncate ...)).
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(define_insn "*cond_uxt<mode>_2"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_FULL_I
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl")
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(and:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand" "0, w")
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(match_operand:SVE_FULL_I 3 "aarch64_sve_uxt_immediate"))
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(and:SVE_I
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(match_operand:SVE_I 2 "register_operand" "0, w")
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(match_operand:SVE_I 3 "aarch64_sve_uxt_immediate"))
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(match_dup 2)]
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UNSPEC_SEL))]
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"TARGET_SVE"
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@ -3159,13 +3159,13 @@
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;; as early-clobber helps to make the instruction more regular to the
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;; register allocator.
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(define_insn "*cond_uxt<mode>_any"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=&w, ?&w, ?&w")
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(unspec:SVE_FULL_I
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[(set (match_operand:SVE_I 0 "register_operand" "=&w, ?&w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl")
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(and:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand" "w, w, w")
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(match_operand:SVE_FULL_I 3 "aarch64_sve_uxt_immediate"))
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(match_operand:SVE_FULL_I 4 "aarch64_simd_reg_or_zero" "0, Dz, w")]
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(and:SVE_I
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(match_operand:SVE_I 2 "register_operand" "w, w, w")
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(match_operand:SVE_I 3 "aarch64_sve_uxt_immediate"))
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(match_operand:SVE_I 4 "aarch64_simd_reg_or_zero" "0, Dz, w")]
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UNSPEC_SEL))]
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"TARGET_SVE && !rtx_equal_p (operands[2], operands[4])"
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"@
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33
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_5.c
Normal file
33
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_5.c
Normal file
@ -0,0 +1,33 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include <stdint.h>
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#define DEF_LOOP(TYPE1, TYPE2, CONST, COUNT) \
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void __attribute__ ((noipa)) \
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test_##CONST##_##TYPE1##_##TYPE2 (TYPE2 *restrict r, \
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TYPE1 *restrict a, \
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TYPE2 *restrict b) \
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{ \
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for (int i = 0; i < COUNT; ++i) \
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r[i] = a[i] > 20 ? b[i] & CONST : b[i]; \
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}
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#define TEST_ALL(T) \
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T (int32_t, uint16_t, 0xff, 3) \
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\
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T (int64_t, uint16_t, 0xff, 5) \
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T (int64_t, uint32_t, 0xff, 5) \
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T (int64_t, uint32_t, 0xffff, 5)
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TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x2[],][^L]*\tuxtb\t\1\.h, p[0-7]/m, \1\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x2[],][^L]*\tuxtb\t\1\.h, p[0-7]/m, \1\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x2[],][^L]*\tuxtb\t\1\.s, p[0-7]/m, \1\.s\n} } } */
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/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x2[],][^L]*\tuxth\t\1\.s, p[0-7]/m, \1\.s\n} } } */
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/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */
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/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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26
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_5_run.c
Normal file
26
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_5_run.c
Normal file
@ -0,0 +1,26 @@
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/* { dg-do run { target { aarch64_sve_hw } } } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include "cond_uxt_5.c"
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#define TEST_LOOP(TYPE1, TYPE2, CONST, N) \
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{ \
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TYPE1 a[N]; \
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TYPE2 r[N], b[N]; \
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for (int i = 0; i < N; ++i) \
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{ \
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a[i] = (i & 1 ? -20 - i : 20 + i); \
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b[i] = -5 - i; \
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asm volatile ("" ::: "memory"); \
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} \
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test_##CONST##_##TYPE1##_##TYPE2 (r, a, b); \
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for (int i = 0; i < N; ++i) \
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if (r[i] != (TYPE2) (a[i] > 20 ? b[i] & CONST : b[i])) \
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__builtin_abort (); \
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}
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int main ()
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{
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TEST_ALL (TEST_LOOP)
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return 0;
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}
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33
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_6.c
Normal file
33
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_6.c
Normal file
@ -0,0 +1,33 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include <stdint.h>
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#define DEF_LOOP(TYPE1, TYPE2, CONST, COUNT) \
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void __attribute__ ((noipa)) \
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test_##CONST##_##TYPE1##_##TYPE2 (TYPE2 *restrict r, \
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TYPE1 *restrict a, \
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TYPE2 *restrict b) \
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{ \
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for (int i = 0; i < COUNT; ++i) \
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r[i] = a[i] > 20 ? b[i] & CONST : a[i]; \
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}
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#define TEST_ALL(T) \
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T (int32_t, uint16_t, 0xff, 3) \
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\
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T (int64_t, uint16_t, 0xff, 5) \
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T (int64_t, uint32_t, 0xff, 5) \
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T (int64_t, uint32_t, 0xffff, 5)
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TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler {\tld1w\t(z[0-9]+)\.s, p[0-7]/z, \[x1[],][^L]*\tld1h\t(z[0-9]+)\.s, p[0-7]/z, \[x2[],][^L]*\tuxtb\t\1\.h, p[0-7]/m, \2\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1d\t(z[0-9]+)\.d, p[0-7]/z, \[x1[],][^L]*\tld1h\t(z[0-9]+)\.d, p[0-7]/z, \[x2[],][^L]*\tuxtb\t\1\.h, p[0-7]/m, \2\.h\n} } } */
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/* { dg-final { scan-assembler {\tld1d\t(z[0-9]+)\.d, p[0-7]/z, \[x1[],][^L]*\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x2[],][^L]*\tuxtb\t\1\.s, p[0-7]/m, \2\.s\n} } } */
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/* { dg-final { scan-assembler {\tld1d\t(z[0-9]+)\.d, p[0-7]/z, \[x1[],][^L]*\tld1w\t(z[0-9]+)\.d, p[0-7]/z, \[x2[],][^L]*\tuxth\t\1\.s, p[0-7]/m, \2\.s\n} } } */
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/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */
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/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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26
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_6_run.c
Normal file
26
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_6_run.c
Normal file
@ -0,0 +1,26 @@
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/* { dg-do run { target { aarch64_sve_hw } } } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include "cond_uxt_6.c"
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#define TEST_LOOP(TYPE1, TYPE2, CONST, N) \
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{ \
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TYPE1 a[N]; \
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TYPE2 r[N], b[N]; \
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for (int i = 0; i < N; ++i) \
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{ \
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a[i] = (i & 1 ? -20 - i : 20 + i); \
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b[i] = -5 - i; \
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asm volatile ("" ::: "memory"); \
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} \
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test_##CONST##_##TYPE1##_##TYPE2 (r, a, b); \
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for (int i = 0; i < N; ++i) \
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if (r[i] != (TYPE2) (a[i] > 20 ? b[i] & CONST : a[i])) \
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__builtin_abort (); \
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}
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int main ()
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{
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TEST_ALL (TEST_LOOP)
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return 0;
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}
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29
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_7.c
Normal file
29
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_7.c
Normal file
@ -0,0 +1,29 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include <stdint.h>
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#define DEF_LOOP(TYPE1, TYPE2, CONST, COUNT) \
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void __attribute__ ((noipa)) \
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test_##CONST##_##TYPE1##_##TYPE2 (TYPE2 *restrict r, \
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TYPE1 *restrict a, \
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TYPE2 *restrict b) \
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{ \
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for (int i = 0; i < COUNT; ++i) \
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r[i] = a[i] > 20 ? b[i] & CONST : 127; \
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}
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#define TEST_ALL(T) \
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T (int32_t, uint16_t, 0xff, 3) \
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\
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T (int64_t, uint16_t, 0xff, 5) \
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T (int64_t, uint32_t, 0xff, 5) \
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T (int64_t, uint32_t, 0xffff, 5)
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TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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26
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_7_run.c
Normal file
26
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_7_run.c
Normal file
@ -0,0 +1,26 @@
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/* { dg-do run { target { aarch64_sve_hw } } } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include "cond_uxt_7.c"
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#define TEST_LOOP(TYPE1, TYPE2, CONST, N) \
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{ \
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TYPE1 a[N]; \
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TYPE2 r[N], b[N]; \
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for (int i = 0; i < N; ++i) \
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{ \
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a[i] = (i & 1 ? -20 - i : 20 + i); \
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b[i] = -5 - i; \
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asm volatile ("" ::: "memory"); \
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} \
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test_##CONST##_##TYPE1##_##TYPE2 (r, a, b); \
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for (int i = 0; i < N; ++i) \
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if (r[i] != (TYPE2) (a[i] > 20 ? b[i] & CONST : 127)) \
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__builtin_abort (); \
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}
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int main ()
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{
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TEST_ALL (TEST_LOOP)
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return 0;
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}
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32
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_8.c
Normal file
32
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_8.c
Normal file
@ -0,0 +1,32 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include <stdint.h>
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#define DEF_LOOP(TYPE1, TYPE2, CONST, COUNT) \
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void __attribute__ ((noipa)) \
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test_##CONST##_##TYPE1##_##TYPE2 (TYPE2 *restrict r, \
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TYPE1 *restrict a, \
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TYPE2 *restrict b) \
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{ \
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for (int i = 0; i < COUNT; ++i) \
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r[i] = a[i] > 20 ? b[i] & CONST : 0; \
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}
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#define TEST_ALL(T) \
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T (int32_t, uint16_t, 0xff, 3) \
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\
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T (int64_t, uint16_t, 0xff, 5) \
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T (int64_t, uint32_t, 0xff, 5) \
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T (int64_t, uint32_t, 0xffff, 5)
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TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tuxtb\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tuxth\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler {\tmovprfx\tz[^,]*, p[0-7]/z} } } */
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/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */
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/* { dg-final { scan-assembler-not {\tsel\t} } } */
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26
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_8_run.c
Normal file
26
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_8_run.c
Normal file
@ -0,0 +1,26 @@
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/* { dg-do run { target { aarch64_sve_hw } } } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include "cond_uxt_8.c"
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#define TEST_LOOP(TYPE1, TYPE2, CONST, N) \
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{ \
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TYPE1 a[N]; \
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TYPE2 r[N], b[N]; \
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for (int i = 0; i < N; ++i) \
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{ \
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a[i] = (i & 1 ? -20 - i : 20 + i); \
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b[i] = -5 - i; \
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asm volatile ("" ::: "memory"); \
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} \
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test_##CONST##_##TYPE1##_##TYPE2 (r, a, b); \
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for (int i = 0; i < N; ++i) \
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if (r[i] != (TYPE2) (a[i] > 20 ? b[i] & CONST : 0)) \
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__builtin_abort (); \
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}
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int main ()
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{
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TEST_ALL (TEST_LOOP)
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return 0;
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}
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