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re PR target/51244 ([SH] Inefficient conditional branch and code around T bit)

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PR target/51244
	* config/sh/sh.opt (mzdcbranch): New option.
	* doc/invoke.texi: Document it.
	* config/sh/sh.md (negsi_cond): Use TARGET_ZDCBRANCH as condition
	instead of TARGET_HARD_SH4.
	* config/sh/sh.c (sh_option_override): Set TARGET_ZDCBRANCH as default
	for TARGET_HARD_SH4.

From-SVN: r189877
This commit is contained in:
Oleg Endo 2012-07-26 00:19:58 +00:00
parent 3b29b58c1b
commit f34ee0b290
5 changed files with 33 additions and 4 deletions
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10
gcc/ChangeLog
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@ -1,3 +1,13 @@
2012-07-26 Oleg Endo <olegendo@gcc.gnu.org>
PR target/51244
* config/sh/sh.opt (mzdcbranch): New option.
* doc/invoke.texi: Document it.
* config/sh/sh.md (negsi_cond): Use TARGET_ZDCBRANCH as condition
instead of TARGET_HARD_SH4.
* config/sh/sh.c (sh_option_override): Set TARGET_ZDCBRANCH as default
for TARGET_HARD_SH4.
2012-07-25 Oleg Endo <olegendo@gcc.gnu.org>
PR target/54089

4
gcc/config/sh/sh.c
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@ -741,6 +741,10 @@ sh_option_override (void)
sh_branch_cost = 2;
}
/* Set -mzdcbranch for SH4 / SH4A if not otherwise specified by the user. */
if (! global_options_set.x_TARGET_ZDCBRANCH && TARGET_HARD_SH4)
TARGET_ZDCBRANCH = 1;
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
if (! VALID_REGISTER_P (regno))
sh_register_names[regno][0] = '\0';

4
gcc/config/sh/sh.md
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@ -4378,11 +4378,11 @@ label:
(match_operand:SI 3 "const_int_operand" "M,N"))
(match_operand:SI 1 "arith_reg_operand" "0,0")
(neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
"TARGET_HARD_SH4"
"TARGET_SH1 && TARGET_ZDCBRANCH"
"@
bt\\t0f\;neg\\t%2,%0\\n0:
bf\\t0f\;neg\\t%2,%0\\n0:"
"!TARGET_HARD_SH4"
"TARGET_SH1 && ! TARGET_ZDCBRANCH"
[(const_int 0)]
{
rtx skip_neg_label = gen_label_rtx ();

4
gcc/config/sh/sh.opt
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@ -225,6 +225,10 @@ mbranch-cost=
Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1)
Cost to assume for a branch insn
mzdcbranch
Target Var(TARGET_ZDCBRANCH)
Assume that zero displacement conditional branches are fast
mcbranchdi
Target Var(TARGET_CBRANCHDI4)
Enable cbranchdi4 pattern

15
gcc/doc/invoke.texi
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@ -889,8 +889,9 @@ See RS/6000 and PowerPC Options.
-mdivsi3_libfunc=@var{name} -mfixed-range=@var{register-range} @gol
-mindexed-addressing -mgettrcost=@var{number} -mpt-fixed @gol
-maccumulate-outgoing-args -minvalid-symbols -msoft-atomic -mhard-atomic @gol
-mbranch-cost=@var{num} -mcbranchdi -mcmpeqdi -mfused-madd -mno-fused-madd @gol
-mfsca -mno-fsca -mfsrra -mno-fsrra -mpretend-cmove -menable-tas}
-mbranch-cost=@var{num} -mzdcbranch -mno-zdcbranch -mcbranchdi -mcmpeqdi @gol
-mfused-madd -mno-fused-madd -mfsca -mno-fsca -mfsrra -mno-fsrra @gol
-mpretend-cmove -menable-tas}
@emph{Solaris 2 Options}
@gccoptlist{-mimpure-text -mno-impure-text @gol
@ -18366,6 +18367,16 @@ make the compiler try to generate more branch-free code if possible.
If not specified the value is selected depending on the processor type that
is being compiled for.
@item -mzdcbranch
@itemx -mno-zdcbranch
@opindex mzdcbranch
@opindex mno-zdcbranch
Assume (do not assume) that zero displacement conditional branch instructions
@code{bt} and @code{bf} are fast. If @option{-mzdcbranch} is specified, the
compiler will try to prefer zero displacement branch code sequences. This is
enabled by default when generating code for SH4 and SH4A. It can be explicitly
disabled by specifying @option{-mno-zdcbranch}.
@item -mcbranchdi
@opindex mcbranchdi
Enable the @code{cbranchdi4} instruction pattern.