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[GCC][PATCH][ARM]Add ACLE intrinsics for dot product (vusdot - vector, v<us/su>dot - by element) for AArch32 AdvSIMD ARMv8.6 Extension
This patch adds the ARMv8.6 Extension ACLE intrinsics for dot product operations (vector/by element) to the ARM back-end. These are: usdot (vector), <us/su>dot (by element). The functions are optional from ARMv8.2-a as -march=armv8.2-a+i8mm and for ARM they remain optional after as of ARMv8.6-a. The functions are declared in arm_neon.h, RTL patterns are defined to generate assembler and tests are added to verify and perform adequate checks. Regression testing on arm-none-eabi passed successfully. gcc/ChangeLog: 2020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com> * config/arm/arm-builtins.c (enum arm_type_qualifiers): (USTERNOP_QUALIFIERS): New define. (USMAC_LANE_QUADTUP_QUALIFIERS): New define. (SUMAC_LANE_QUADTUP_QUALIFIERS): New define. (arm_expand_builtin_args): Add case ARG_BUILTIN_LANE_QUADTUP_INDEX. (arm_expand_builtin_1): Add qualifier_lane_quadtup_index. * config/arm/arm_neon.h (vusdot_s32): New. (vusdot_lane_s32): New. (vusdotq_lane_s32): New. (vsudot_lane_s32): New. (vsudotq_lane_s32): New. * config/arm/arm_neon_builtins.def (usdot, usdot_lane,sudot_lane): New. * config/arm/iterators.md (DOTPROD_I8MM): New. (sup, opsuffix): Add <us/su>. * config/arm/neon.md (neon_usdot, <us/su>dot_lane: New. * config/arm/unspecs.md (UNSPEC_DOT_US, UNSPEC_DOT_SU): New. gcc/testsuite/ChangeLog: 2020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com> * gcc.target/arm/simd/vdot-2-1.c: New test. * gcc.target/arm/simd/vdot-2-2.c: New test. * gcc.target/arm/simd/vdot-2-3.c: New test. * gcc.target/arm/simd/vdot-2-4.c: New test.
This commit is contained in:
Stam Markianos-Wright
parent
667afe5a49
commit
f348846e25
@ -1,3 +1,22 @@
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2020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com>
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* config/arm/arm-builtins.c (enum arm_type_qualifiers):
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(USTERNOP_QUALIFIERS): New define.
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(USMAC_LANE_QUADTUP_QUALIFIERS): New define.
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(SUMAC_LANE_QUADTUP_QUALIFIERS): New define.
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(arm_expand_builtin_args): Add case ARG_BUILTIN_LANE_QUADTUP_INDEX.
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(arm_expand_builtin_1): Add qualifier_lane_quadtup_index.
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* config/arm/arm_neon.h (vusdot_s32): New.
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(vusdot_lane_s32): New.
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(vusdotq_lane_s32): New.
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(vsudot_lane_s32): New.
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(vsudotq_lane_s32): New.
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* config/arm/arm_neon_builtins.def (usdot, usdot_lane,sudot_lane): New.
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* config/arm/iterators.md (DOTPROD_I8MM): New.
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(sup, opsuffix): Add <us/su>.
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* config/arm/neon.md (neon_usdot, <us/su>dot_lane: New.
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* config/arm/unspecs.md (UNSPEC_DOT_US, UNSPEC_DOT_SU): New.
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2020-02-11 Richard Biener <rguenther@suse.de>
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PR tree-optimization/93661
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@ -86,7 +86,10 @@ enum arm_type_qualifiers
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qualifier_const_void_pointer = 0x802,
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/* Lane indices selected in pairs - must be within range of previous
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argument = a vector. */
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qualifier_lane_pair_index = 0x1000
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qualifier_lane_pair_index = 0x1000,
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/* Lane indices selected in quadtuplets - must be within range of previous
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argument = a vector. */
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qualifier_lane_quadtup_index = 0x2000
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};
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/* The qualifier_internal allows generation of a unary builtin from
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@ -122,6 +125,13 @@ arm_unsigned_uternop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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qualifier_unsigned };
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#define UTERNOP_QUALIFIERS (arm_unsigned_uternop_qualifiers)
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/* T (T, unsigned T, T). */
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static enum arm_type_qualifiers
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arm_usternop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_none, qualifier_none, qualifier_unsigned,
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qualifier_none };
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#define USTERNOP_QUALIFIERS (arm_usternop_qualifiers)
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/* T (T, immediate). */
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static enum arm_type_qualifiers
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arm_binop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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@ -176,6 +186,20 @@ arm_umac_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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qualifier_unsigned, qualifier_lane_index };
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#define UMAC_LANE_QUALIFIERS (arm_umac_lane_qualifiers)
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/* T (T, unsigned T, T, lane index). */
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static enum arm_type_qualifiers
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arm_usmac_lane_quadtup_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_none, qualifier_none, qualifier_unsigned,
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qualifier_none, qualifier_lane_quadtup_index };
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#define USMAC_LANE_QUADTUP_QUALIFIERS (arm_usmac_lane_quadtup_qualifiers)
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/* T (T, T, unsigend T, lane index). */
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static enum arm_type_qualifiers
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arm_sumac_lane_quadtup_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_none, qualifier_none, qualifier_none,
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qualifier_unsigned, qualifier_lane_quadtup_index };
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#define SUMAC_LANE_QUADTUP_QUALIFIERS (arm_sumac_lane_quadtup_qualifiers)
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/* T (T, T, immediate). */
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static enum arm_type_qualifiers
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arm_ternop_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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@ -2177,6 +2201,7 @@ typedef enum {
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ARG_BUILTIN_LANE_INDEX,
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ARG_BUILTIN_STRUCT_LOAD_STORE_LANE_INDEX,
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ARG_BUILTIN_LANE_PAIR_INDEX,
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ARG_BUILTIN_LANE_QUADTUP_INDEX,
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ARG_BUILTIN_NEON_MEMORY,
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ARG_BUILTIN_MEMORY,
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ARG_BUILTIN_STOP
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@ -2325,11 +2350,24 @@ arm_expand_builtin_args (rtx target, machine_mode map_mode, int fcode,
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if (CONST_INT_P (op[argc]))
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{
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machine_mode vmode = mode[argc - 1];
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neon_lane_bounds (op[argc], 0, GET_MODE_NUNITS (vmode) / 2, exp);
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neon_lane_bounds (op[argc], 0,
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GET_MODE_NUNITS (vmode) / 2, exp);
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}
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/* If the lane index isn't a constant then the next
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case will error. */
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/* Fall through. */
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/* If the lane index isn't a constant then error out. */
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goto constant_arg;
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case ARG_BUILTIN_LANE_QUADTUP_INDEX:
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/* Previous argument must be a vector, which this indexes. */
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gcc_assert (argc > 0);
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if (CONST_INT_P (op[argc]))
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{
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machine_mode vmode = mode[argc - 1];
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neon_lane_bounds (op[argc], 0,
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GET_MODE_NUNITS (vmode) / 4, exp);
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}
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/* If the lane index isn't a constant then error out. */
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goto constant_arg;
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case ARG_BUILTIN_CONSTANT:
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constant_arg:
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if (!(*insn_data[icode].operand[opno].predicate)
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@ -2493,6 +2531,8 @@ arm_expand_builtin_1 (int fcode, tree exp, rtx target,
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args[k] = ARG_BUILTIN_LANE_INDEX;
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else if (d->qualifiers[qualifiers_k] & qualifier_lane_pair_index)
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args[k] = ARG_BUILTIN_LANE_PAIR_INDEX;
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else if (d->qualifiers[qualifiers_k] & qualifier_lane_quadtup_index)
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args[k] = ARG_BUILTIN_LANE_QUADTUP_INDEX;
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else if (d->qualifiers[qualifiers_k] & qualifier_struct_load_store_lane_index)
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args[k] = ARG_BUILTIN_STRUCT_LOAD_STORE_LANE_INDEX;
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else if (d->qualifiers[qualifiers_k] & qualifier_immediate)
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@ -18742,6 +18742,52 @@ vcmlaq_rot270_laneq_f32 (float32x4_t __r, float32x4_t __a, float32x4_t __b,
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return __builtin_neon_vcmla_lane270v4sf (__r, __a, __b, __index);
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}
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/* AdvSIMD Matrix Multiply-Accumulate and Dot Product intrinsics. */
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#pragma GCC push_options
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#pragma GCC target ("arch=armv8.2-a+i8mm")
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__extension__ extern __inline int32x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vusdot_s32 (int32x2_t __r, uint8x8_t __a, int8x8_t __b)
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{
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return __builtin_neon_usdotv8qi_ssus (__r, __a, __b);
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}
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__extension__ extern __inline int32x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vusdot_lane_s32 (int32x2_t __r, uint8x8_t __a,
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int8x8_t __b, const int __index)
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{
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return __builtin_neon_usdot_lanev8qi_ssuss (__r, __a, __b, __index);
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}
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__extension__ extern __inline int32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vusdotq_lane_s32 (int32x4_t __r, uint8x16_t __a,
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int8x8_t __b, const int __index)
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{
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return __builtin_neon_usdot_lanev16qi_ssuss (__r, __a, __b, __index);
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}
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__extension__ extern __inline int32x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vsudot_lane_s32 (int32x2_t __r, int8x8_t __a,
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uint8x8_t __b, const int __index)
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{
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return __builtin_neon_sudot_lanev8qi_sssus (__r, __a, __b, __index);
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}
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__extension__ extern __inline int32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vsudotq_lane_s32 (int32x4_t __r, int8x16_t __a,
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uint8x8_t __b, const int __index)
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{
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return __builtin_neon_sudot_lanev16qi_sssus (__r, __a, __b, __index);
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}
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#pragma GCC pop_options
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#pragma GCC pop_options
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#endif
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@ -352,6 +352,10 @@ VAR2 (UTERNOP, udot, v8qi, v16qi)
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VAR2 (MAC_LANE, sdot_lane, v8qi, v16qi)
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VAR2 (UMAC_LANE, udot_lane, v8qi, v16qi)
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VAR1 (USTERNOP, usdot, v8qi)
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VAR2 (USMAC_LANE_QUADTUP, usdot_lane, v8qi, v16qi)
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VAR2 (SUMAC_LANE_QUADTUP, sudot_lane, v8qi, v16qi)
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VAR4 (BINOP, vcadd90, v4hf, v2sf, v8hf, v4sf)
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VAR4 (BINOP, vcadd270, v4hf, v2sf, v8hf, v4sf)
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VAR4 (TERNOP, vcmla0, v2sf, v4sf, v4hf, v8hf)
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@ -480,6 +480,8 @@
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(define_int_iterator DOTPROD [UNSPEC_DOT_S UNSPEC_DOT_U])
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(define_int_iterator DOTPROD_I8MM [UNSPEC_DOT_US UNSPEC_DOT_SU])
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(define_int_iterator VFMLHALVES [UNSPEC_VFML_LO UNSPEC_VFML_HI])
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(define_int_iterator VCADD [UNSPEC_VCADD90 UNSPEC_VCADD270])
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@ -938,6 +940,7 @@
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(UNSPEC_VRSRA_S_N "s") (UNSPEC_VRSRA_U_N "u")
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(UNSPEC_VCVTH_S "s") (UNSPEC_VCVTH_U "u")
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(UNSPEC_DOT_S "s") (UNSPEC_DOT_U "u")
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(UNSPEC_DOT_US "us") (UNSPEC_DOT_SU "su")
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(UNSPEC_SSAT16 "s") (UNSPEC_USAT16 "u")
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])
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@ -1169,6 +1172,9 @@
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(define_int_attr MRRC [(VUNSPEC_MRRC "MRRC") (VUNSPEC_MRRC2 "MRRC2")])
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(define_int_attr opsuffix [(UNSPEC_DOT_S "s8")
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(UNSPEC_DOT_U "u8")])
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(UNSPEC_DOT_U "u8")
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(UNSPEC_DOT_US "s8")
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(UNSPEC_DOT_SU "u8")
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])
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(define_int_attr smlaw_op [(UNSPEC_SMLAWB "smlawb") (UNSPEC_SMLAWT "smlawt")])
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@ -3279,6 +3279,20 @@
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[(set_attr "type" "neon_dot<q>")]
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)
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;; These instructions map to the __builtins for the Dot Product operations.
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(define_insn "neon_usdot<vsi2qi>"
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[(set (match_operand:VCVTI 0 "register_operand" "=w")
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(plus:VCVTI
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(unspec:VCVTI
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[(match_operand:<VSI2QI> 2 "register_operand" "w")
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(match_operand:<VSI2QI> 3 "register_operand" "w")]
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UNSPEC_DOT_US)
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(match_operand:VCVTI 1 "register_operand" "0")))]
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"TARGET_I8MM"
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"vusdot.s8\\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
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[(set_attr "type" "neon_dot<q>")]
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)
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;; These instructions map to the __builtins for the Dot Product
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;; indexed operations.
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(define_insn "neon_<sup>dot_lane<vsi2qi>"
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@ -3298,6 +3312,25 @@
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[(set_attr "type" "neon_dot<q>")]
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)
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;; These instructions map to the __builtins for the Dot Product
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;; indexed operations in the v8.6 I8MM extension.
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(define_insn "neon_<sup>dot_lane<vsi2qi>"
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[(set (match_operand:VCVTI 0 "register_operand" "=w")
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(plus:VCVTI
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(unspec:VCVTI
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[(match_operand:<VSI2QI> 2 "register_operand" "w")
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(match_operand:V8QI 3 "register_operand" "t")
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(match_operand:SI 4 "immediate_operand" "i")]
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DOTPROD_I8MM)
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(match_operand:VCVTI 1 "register_operand" "0")))]
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"TARGET_I8MM"
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{
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operands[4] = GEN_INT (INTVAL (operands[4]));
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return "v<sup>dot.<opsuffix>\\t%<V_reg>0, %<V_reg>2, %P3[%c4]";
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}
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[(set_attr "type" "neon_dot<q>")]
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)
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;; These expands map to the Dot Product optab the vectorizer checks for.
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;; The auto-vectorizer expects a dot product builtin that also does an
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;; accumulation into the provided register.
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@ -493,6 +493,8 @@
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UNSPEC_VRNDX
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UNSPEC_DOT_S
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UNSPEC_DOT_U
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UNSPEC_DOT_US
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UNSPEC_DOT_SU
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UNSPEC_VFML_LO
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UNSPEC_VFML_HI
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UNSPEC_VCADD90
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@ -1,3 +1,10 @@
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2020-02-11 Stam Markianos-Wright <stam.markianos-wright@arm.com>
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* gcc.target/arm/simd/vdot-2-1.c: New test.
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* gcc.target/arm/simd/vdot-2-2.c: New test.
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* gcc.target/arm/simd/vdot-2-3.c: New test.
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* gcc.target/arm/simd/vdot-2-4.c: New test.
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2020-02-11 Richard Biener <rguenther@suse.de>
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PR tree-optimization/93661
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91
gcc/testsuite/gcc.target/arm/simd/vdot-2-1.c
Normal file
91
gcc/testsuite/gcc.target/arm/simd/vdot-2-1.c
Normal file
@ -0,0 +1,91 @@
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/* { dg-do assemble { target { arm*-*-* } } } */
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/* { dg-require-effective-target arm_v8_2a_i8mm_ok } */
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/* { dg-add-options arm_v8_2a_i8mm } */
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/* { dg-additional-options "-O -save-temps" } */
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/* { dg-final { check-function-bodies "**" "" } } */
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#include <arm_neon.h>
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/* Unsigned-Signed Dot Product instructions. */
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/*
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**usfoo:
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** ...
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** vusdot\.s8 d0, d1, d2
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** bx lr
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*/
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int32x2_t usfoo (int32x2_t r, uint8x8_t x, int8x8_t y)
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{
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return vusdot_s32 (r, x, y);
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}
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/*
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**usfoo_lane:
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** ...
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** vusdot\.s8 d0, d1, d2\[0\]
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** bx lr
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*/
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int32x2_t usfoo_lane (int32x2_t r, uint8x8_t x, int8x8_t y)
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{
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return vusdot_lane_s32 (r, x, y, 0);
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}
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/*
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**usfooq_lane:
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** ...
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** vusdot\.s8 q0, q1, d4\[1\]
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** bx lr
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*/
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int32x4_t usfooq_lane (int32x4_t r, uint8x16_t x, int8x8_t y)
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{
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return vusdotq_lane_s32 (r, x, y, 1);
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}
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/* Signed-Unsigned Dot Product instructions. */
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/*
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**sfoo_lane:
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** ...
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** vsudot\.u8 d0, d1, d2\[0\]
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** bx lr
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*/
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int32x2_t sfoo_lane (int32x2_t r, int8x8_t x, uint8x8_t y)
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{
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return vsudot_lane_s32 (r, x, y, 0);
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}
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/*
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**sfooq_lane:
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** ...
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** vsudot\.u8 q0, q1, d4\[1\]
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** bx lr
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*/
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int32x4_t sfooq_lane (int32x4_t r, int8x16_t x, uint8x8_t y)
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{
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return vsudotq_lane_s32 (r, x, y, 1);
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}
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/*
|
||||
**usfoo_untied:
|
||||
** ...
|
||||
** vusdot\.s8 d1, d2, d3
|
||||
** vmov d0, d1 @ v2si
|
||||
** bx lr
|
||||
*/
|
||||
int32x2_t usfoo_untied (int32x2_t unused, int32x2_t r, uint8x8_t x, int8x8_t y)
|
||||
{
|
||||
return vusdot_s32 (r, x, y);
|
||||
}
|
||||
|
||||
/*
|
||||
**usfoo_lane_untied:
|
||||
** ...
|
||||
** vusdot.s8 d1, d2, d3\[0\]
|
||||
** vmov d0, d1 @ v2si
|
||||
** bx lr
|
||||
*/
|
||||
int32x2_t usfoo_lane_untied (int32x2_t unused, int32x2_t r, uint8x8_t x, int8x8_t y)
|
||||
{
|
||||
return vusdot_lane_s32 (r, x, y, 0);
|
||||
}
|
||||
|
||||
90
gcc/testsuite/gcc.target/arm/simd/vdot-2-2.c
Normal file
90
gcc/testsuite/gcc.target/arm/simd/vdot-2-2.c
Normal file
@ -0,0 +1,90 @@
|
||||
/* { dg-do assemble { target { arm*-*-* } } } */
|
||||
/* { dg-require-effective-target arm_v8_2a_i8mm_ok } */
|
||||
/* { dg-add-options arm_v8_2a_i8mm } */
|
||||
/* { dg-additional-options "-O -save-temps -mbig-endian" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
|
||||
/* Unsigned-Signed Dot Product instructions. */
|
||||
|
||||
/*
|
||||
**usfoo:
|
||||
** ...
|
||||
** vusdot\.s8 d0, d1, d2
|
||||
** bx lr
|
||||
*/
|
||||
int32x2_t usfoo (int32x2_t r, uint8x8_t x, int8x8_t y)
|
||||
{
|
||||
return vusdot_s32 (r, x, y);
|
||||
}
|
||||
|
||||
/*
|
||||
**usfoo_lane:
|
||||
** ...
|
||||
** vusdot\.s8 d0, d1, d2\[0\]
|
||||
** bx lr
|
||||
*/
|
||||
int32x2_t usfoo_lane (int32x2_t r, uint8x8_t x, int8x8_t y)
|
||||
{
|
||||
return vusdot_lane_s32 (r, x, y, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
**usfooq_lane:
|
||||
** ...
|
||||
** vusdot\.s8 q0, q1, d4\[1\]
|
||||
** bx lr
|
||||
*/
|
||||
int32x4_t usfooq_lane (int32x4_t r, uint8x16_t x, int8x8_t y)
|
||||
{
|
||||
return vusdotq_lane_s32 (r, x, y, 1);
|
||||
}
|
||||
|
||||
/* Signed-Unsigned Dot Product instructions. */
|
||||
|
||||
/*
|
||||
**sfoo_lane:
|
||||
** ...
|
||||
** vsudot\.u8 d0, d1, d2\[0\]
|
||||
** bx lr
|
||||
*/
|
||||
int32x2_t sfoo_lane (int32x2_t r, int8x8_t x, uint8x8_t y)
|
||||
{
|
||||
return vsudot_lane_s32 (r, x, y, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
**sfooq_lane:
|
||||
** ...
|
||||
** vsudot\.u8 q0, q1, d4\[1\]
|
||||
** bx lr
|
||||
*/
|
||||
int32x4_t sfooq_lane (int32x4_t r, int8x16_t x, uint8x8_t y)
|
||||
{
|
||||
return vsudotq_lane_s32 (r, x, y, 1);
|
||||
}
|
||||
|
||||
/*
|
||||
**usfoo_untied:
|
||||
** ...
|
||||
** vusdot\.s8 d1, d2, d3
|
||||
** vmov d0, d1 @ v2si
|
||||
** bx lr
|
||||
*/
|
||||
int32x2_t usfoo_untied (int32x2_t unused, int32x2_t r, uint8x8_t x, int8x8_t y)
|
||||
{
|
||||
return vusdot_s32 (r, x, y);
|
||||
}
|
||||
|
||||
/*
|
||||
**usfoo_lane_untied:
|
||||
** ...
|
||||
** vusdot.s8 d1, d2, d3\[0\]
|
||||
** vmov d0, d1 @ v2si
|
||||
** bx lr
|
||||
*/
|
||||
int32x2_t usfoo_lane_untied (int32x2_t unused, int32x2_t r, uint8x8_t x, int8x8_t y)
|
||||
{
|
||||
return vusdot_lane_s32 (r, x, y, 0);
|
||||
}
|
||||
21
gcc/testsuite/gcc.target/arm/simd/vdot-2-3.c
Normal file
21
gcc/testsuite/gcc.target/arm/simd/vdot-2-3.c
Normal file
@ -0,0 +1,21 @@
|
||||
/* { dg-do assemble { target { arm*-*-* } } } */
|
||||
/* { dg-require-effective-target arm_v8_2a_i8mm_ok } */
|
||||
/* { dg-add-options arm_v8_2a_i8mm } */
|
||||
/* { dg-additional-options "--save-temps" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
|
||||
/* Unsigned-Signed Dot Product instructions. */
|
||||
|
||||
int32x2_t usfoo_lane (int32x2_t r, uint8x8_t x, int8x8_t y)
|
||||
{
|
||||
/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
|
||||
return vusdot_lane_s32 (r, x, y, -1);
|
||||
}
|
||||
|
||||
|
||||
int32x4_t usfooq_lane (int32x4_t r, uint8x16_t x, int8x8_t y)
|
||||
{
|
||||
/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
|
||||
return vusdotq_lane_s32 (r, x, y, 2);
|
||||
}
|
||||
20
gcc/testsuite/gcc.target/arm/simd/vdot-2-4.c
Normal file
20
gcc/testsuite/gcc.target/arm/simd/vdot-2-4.c
Normal file
@ -0,0 +1,20 @@
|
||||
/* { dg-do assemble { target { arm*-*-* } } } */
|
||||
/* { dg-require-effective-target arm_v8_2a_i8mm_ok } */
|
||||
/* { dg-add-options arm_v8_2a_i8mm } */
|
||||
/* { dg-additional-options "--save-temps" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
|
||||
/* Signed-Unsigned Dot Product instructions. */
|
||||
|
||||
int32x2_t sfoo_lane (int32x2_t r, int8x8_t x, uint8x8_t y)
|
||||
{
|
||||
/* { dg-error "lane -1 out of range 0 - 1" "" { target *-*-* } 0 } */
|
||||
return vsudot_lane_s32 (r, x, y, -1);
|
||||
}
|
||||
|
||||
int32x4_t sfooq_lane (int32x4_t r, int8x16_t x, uint8x8_t y)
|
||||
{
|
||||
/* { dg-error "lane 2 out of range 0 - 1" "" { target *-*-* } 0 } */
|
||||
return vsudotq_lane_s32 (r, x, y, 2);
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user