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sse.md (sse4_2_pcmpestr_cconly): Prefer pcmpestrm as flags setting insn.
* config/i386/sse.md (sse4_2_pcmpestr_cconly): Prefer pcmpestrm
as flags setting insn.
(sse4_2_pcmpistr_cconly): Prefer pcmpistrm as flags setting insn.
* config/i386/i386.md (UNSPEC_ROUNDP, UNSPEC_ROUNDS): Remove.
(UNSPEC_ROUND): New.
("sse4_1_round<mode>2"): New insn pattern.
("rint<mode>2"): Expand using "sse4_1_round<mode>2" pattern for
SSE4.1 targets.
("floor<mode>2"): Rename from floordf2 and floorsf2. Macroize
expander using SSEMODEF mode macro. Expand using
"sse4_1_round<mode>2" pattern for SSE4.1 targets.
("ceil<mode>2"): Rename from ceildf2 and ceilsf2. Macroize
expander using SSEMODEF mode macro. Expand using
"sse4_1_round<mode>2" pattern for SSE4.1 targets.
("btrunc<mode>2"): Rename from btruncdf2 and btruncsf2. Macroize
expander using SSEMODEF mode macro. Expand using
"sse4_1_round<mode>2" pattern for SSE4.1 targets.
* config/i386/sse.md ("sse4_1_roundpd", "sse4_1_roundps"): Use
UNSPEC_ROUND instead of UNSPEC_ROUNDP.
("sse4_1_roundsd", "sse4_1_roundss"): Use UNSPEC_ROUND instead of
UNSPEC_ROUNDS.
From-SVN: r125356
This commit is contained in:
Uros Bizjak
parent
69f2880c76
commit
f28eb39cee
@ -1,3 +1,30 @@
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2007-06-06 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/sse.md (sse4_2_pcmpestr_cconly): Prefer pcmpestrm
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as flags setting insn.
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(sse4_2_pcmpistr_cconly): Prefer pcmpistrm as flags setting insn.
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2007-06-06 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (UNSPEC_ROUNDP, UNSPEC_ROUNDS): Remove.
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(UNSPEC_ROUND): New.
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("sse4_1_round<mode>2"): New insn pattern.
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("rint<mode>2"): Expand using "sse4_1_round<mode>2" pattern for
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SSE4.1 targets.
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("floor<mode>2"): Rename from floordf2 and floorsf2. Macroize
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expander using SSEMODEF mode macro. Expand using
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"sse4_1_round<mode>2" pattern for SSE4.1 targets.
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("ceil<mode>2"): Rename from ceildf2 and ceilsf2. Macroize
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expander using SSEMODEF mode macro. Expand using
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"sse4_1_round<mode>2" pattern for SSE4.1 targets.
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("btrunc<mode>2"): Rename from btruncdf2 and btruncsf2. Macroize
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expander using SSEMODEF mode macro. Expand using
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"sse4_1_round<mode>2" pattern for SSE4.1 targets.
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* config/i386/sse.md ("sse4_1_roundpd", "sse4_1_roundps"): Use
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UNSPEC_ROUND instead of UNSPEC_ROUNDP.
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("sse4_1_roundsd", "sse4_1_roundss"): Use UNSPEC_ROUND instead of
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UNSPEC_ROUNDS.
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2007-06-06 Jan Sjodin <jan.sjodin@amd.com>
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Sebastian Pop <sebpop@gmail.com>
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@ -53,7 +80,8 @@
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* cfgexpand (label_rtx_for_bb): Likewise.
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(expand_gimple_basic_block): Likewise.
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* cfghooks.c (dump_bb): Likewise.
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(lv_adjust_loop_header_phi): Avoid using C++ keywords as variable names.
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(lv_adjust_loop_header_phi): Avoid using C++ keywords as
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variable names.
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(lv_add_condition_to_bb): Likewise.
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* cfglayout (relink_block_chain): Cast according to the coding
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conventions.
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@ -64,7 +92,8 @@
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(dump_recorded_exit): Likewise.
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* cfgloop.h (enum loop_estimation): Move out of struct scope...
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(struct loop): ... from here.
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* cfgloopmanip.c (rpe_enum_p): Cast according to the coding conventions.
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* cfgloopmanip.c (rpe_enum_p): Cast according to the coding
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conventions.
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* cfgrtl.c (rtl_create_basic_block): Likewise.
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(rtl_split_block): Likewise.
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(rtl_dump_bb): Likewise.
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@ -171,8 +171,7 @@
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(UNSPEC_MPSADBW 138)
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(UNSPEC_PHMINPOSUW 139)
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(UNSPEC_PTEST 140)
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(UNSPEC_ROUNDP 141)
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(UNSPEC_ROUNDS 142)
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(UNSPEC_ROUND 141)
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; For SSE4.2 support
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(UNSPEC_CRC32 143)
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@ -16999,6 +16998,17 @@
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})
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(define_insn "sse4_1_round<mode>2"
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[(set (match_operand:SSEMODEF 0 "register_operand" "=x")
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(unspec:SSEMODEF [(match_operand:SSEMODEF 1 "register_operand" "x")
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(match_operand:SI 2 "const_0_to_15_operand" "n")]
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UNSPEC_ROUND))]
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"TARGET_SSE4_1"
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"rounds<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix_extra" "1")
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(set_attr "mode" "<MODE>")])
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(define_insn "rintxf2"
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[(set (match_operand:XF 0 "register_operand" "=f")
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(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
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@ -17018,12 +17028,18 @@
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&& flag_unsafe_math_optimizations)
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|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
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&& !flag_trapping_math
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&& !optimize_size)"
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&& (TARGET_SSE4_1 || !optimize_size))"
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{
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if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
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&& !flag_trapping_math
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&& !optimize_size)
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ix86_expand_rint (operand0, operand1);
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&& (TARGET_SSE4_1 || !optimize_size))
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{
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if (TARGET_SSE4_1)
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emit_insn (gen_sse4_1_round<mode>2
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(operands[0], operands[1], GEN_INT (0x04)));
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else
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ix86_expand_rint (operand0, operand1);
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}
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else
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{
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rtx op0 = gen_reg_rtx (XFmode);
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@ -17044,7 +17060,7 @@
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&& !flag_trapping_math && !flag_rounding_math
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&& !optimize_size"
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{
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if ((<MODE>mode != DFmode) || TARGET_64BIT)
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if (TARGET_64BIT || (<MODE>mode != DFmode))
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ix86_expand_round (operand0, operand1);
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else
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ix86_expand_rounddf_32 (operand0, operand1);
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@ -17250,20 +17266,25 @@
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DONE;
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})
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(define_expand "floordf2"
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[(use (match_operand:DF 0 "register_operand" ""))
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(use (match_operand:DF 1 "register_operand" ""))]
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"((TARGET_USE_FANCY_MATH_387
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&& (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
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&& flag_unsafe_math_optimizations)
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|| (SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH
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&& !flag_trapping_math))
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&& !optimize_size"
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(define_expand "floor<mode>2"
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[(use (match_operand:SSEMODEF 0 "register_operand" ""))
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(use (match_operand:SSEMODEF 1 "register_operand" ""))]
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"(TARGET_USE_FANCY_MATH_387
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&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
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|| TARGET_MIX_SSE_I387)
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&& flag_unsafe_math_optimizations && !optimize_size)
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|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
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&& !flag_trapping_math
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&& (TARGET_SSE4_1 || !optimize_size))"
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{
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if (SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH
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&& !flag_trapping_math)
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if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
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&& !flag_trapping_math
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&& (TARGET_SSE4_1 || !optimize_size))
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{
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if (TARGET_64BIT)
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if (TARGET_SSE4_1)
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emit_insn (gen_sse4_1_round<mode>2
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(operands[0], operands[1], GEN_INT (0x01)));
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else if (TARGET_64BIT || (<MODE>mode != DFmode))
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ix86_expand_floorceil (operand0, operand1, true);
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else
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ix86_expand_floorceildf_32 (operand0, operand1, true);
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@ -17273,36 +17294,10 @@
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rtx op0 = gen_reg_rtx (XFmode);
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rtx op1 = gen_reg_rtx (XFmode);
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emit_insn (gen_extenddfxf2 (op1, operands[1]));
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emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
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emit_insn (gen_frndintxf2_floor (op0, op1));
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emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
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}
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DONE;
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})
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(define_expand "floorsf2"
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[(use (match_operand:SF 0 "register_operand" ""))
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(use (match_operand:SF 1 "register_operand" ""))]
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"((TARGET_USE_FANCY_MATH_387
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&& (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
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&& flag_unsafe_math_optimizations)
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|| (SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH
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&& !flag_trapping_math))
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&& !optimize_size"
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{
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if (SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH
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&& !flag_trapping_math)
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ix86_expand_floorceil (operand0, operand1, true);
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else
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{
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rtx op0 = gen_reg_rtx (XFmode);
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rtx op1 = gen_reg_rtx (XFmode);
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emit_insn (gen_extendsfxf2 (op1, operands[1]));
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emit_insn (gen_frndintxf2_floor (op0, op1));
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emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
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emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
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}
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DONE;
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})
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@ -17536,20 +17531,25 @@
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DONE;
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})
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(define_expand "ceildf2"
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[(use (match_operand:DF 0 "register_operand" ""))
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(use (match_operand:DF 1 "register_operand" ""))]
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"((TARGET_USE_FANCY_MATH_387
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&& (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
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&& flag_unsafe_math_optimizations)
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|| (SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH
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&& !flag_trapping_math))
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&& !optimize_size"
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(define_expand "ceil<mode>2"
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[(use (match_operand:SSEMODEF 0 "register_operand" ""))
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(use (match_operand:SSEMODEF 1 "register_operand" ""))]
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"(TARGET_USE_FANCY_MATH_387
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&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
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|| TARGET_MIX_SSE_I387)
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&& flag_unsafe_math_optimizations && !optimize_size)
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|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
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&& !flag_trapping_math
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&& (TARGET_SSE4_1 || !optimize_size))"
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{
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if (SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH
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&& !flag_trapping_math)
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if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
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&& !flag_trapping_math
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&& (TARGET_SSE4_1 || !optimize_size))
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{
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if (TARGET_64BIT)
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if (TARGET_SSE4_1)
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emit_insn (gen_sse4_1_round<mode>2
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(operands[0], operands[1], GEN_INT (0x02)));
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else if (TARGET_64BIT || (<MODE>mode != DFmode))
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ix86_expand_floorceil (operand0, operand1, false);
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else
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ix86_expand_floorceildf_32 (operand0, operand1, false);
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@ -17559,36 +17559,10 @@
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rtx op0 = gen_reg_rtx (XFmode);
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rtx op1 = gen_reg_rtx (XFmode);
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emit_insn (gen_extenddfxf2 (op1, operands[1]));
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emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
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emit_insn (gen_frndintxf2_ceil (op0, op1));
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emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
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}
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DONE;
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})
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(define_expand "ceilsf2"
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[(use (match_operand:SF 0 "register_operand" ""))
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(use (match_operand:SF 1 "register_operand" ""))]
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"((TARGET_USE_FANCY_MATH_387
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&& (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
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&& flag_unsafe_math_optimizations)
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|| (SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH
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&& !flag_trapping_math))
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&& !optimize_size"
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{
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if (SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH
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&& !flag_trapping_math)
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ix86_expand_floorceil (operand0, operand1, false);
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else
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{
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rtx op0 = gen_reg_rtx (XFmode);
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rtx op1 = gen_reg_rtx (XFmode);
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emit_insn (gen_extendsfxf2 (op1, operands[1]));
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emit_insn (gen_frndintxf2_ceil (op0, op1));
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emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
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emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
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}
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DONE;
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})
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@ -17820,20 +17794,25 @@
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DONE;
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})
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(define_expand "btruncdf2"
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[(use (match_operand:DF 0 "register_operand" ""))
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(use (match_operand:DF 1 "register_operand" ""))]
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"((TARGET_USE_FANCY_MATH_387
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&& (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)
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&& flag_unsafe_math_optimizations)
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|| (SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH
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&& !flag_trapping_math))
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&& !optimize_size"
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(define_expand "btrunc<mode>2"
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[(use (match_operand:SSEMODEF 0 "register_operand" ""))
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(use (match_operand:SSEMODEF 1 "register_operand" ""))]
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"(TARGET_USE_FANCY_MATH_387
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&& (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
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|| TARGET_MIX_SSE_I387)
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&& flag_unsafe_math_optimizations && !optimize_size)
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|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
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&& !flag_trapping_math
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&& (TARGET_SSE4_1 || !optimize_size))"
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{
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if (SSE_FLOAT_MODE_P (DFmode) && TARGET_SSE_MATH
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&& !flag_trapping_math)
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if (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
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&& !flag_trapping_math
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&& (TARGET_SSE4_1 || !optimize_size))
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{
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if (TARGET_64BIT)
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if (TARGET_SSE4_1)
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emit_insn (gen_sse4_1_round<mode>2
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(operands[0], operands[1], GEN_INT (0x03)));
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else if (TARGET_64BIT || (<MODE>mode != DFmode))
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ix86_expand_trunc (operand0, operand1);
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else
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ix86_expand_truncdf_32 (operand0, operand1);
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@ -17843,36 +17822,10 @@
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rtx op0 = gen_reg_rtx (XFmode);
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rtx op1 = gen_reg_rtx (XFmode);
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emit_insn (gen_extenddfxf2 (op1, operands[1]));
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emit_insn (gen_extend<mode>xf2 (op1, operands[1]));
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emit_insn (gen_frndintxf2_trunc (op0, op1));
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emit_insn (gen_truncxfdf2_i387_noop (operands[0], op0));
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}
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DONE;
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})
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(define_expand "btruncsf2"
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[(use (match_operand:SF 0 "register_operand" ""))
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(use (match_operand:SF 1 "register_operand" ""))]
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"((TARGET_USE_FANCY_MATH_387
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&& (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
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&& flag_unsafe_math_optimizations)
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|| (SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH
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&& !flag_trapping_math))
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&& !optimize_size"
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{
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if (SSE_FLOAT_MODE_P (SFmode) && TARGET_SSE_MATH
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&& !flag_trapping_math)
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ix86_expand_trunc (operand0, operand1);
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else
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{
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rtx op0 = gen_reg_rtx (XFmode);
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rtx op1 = gen_reg_rtx (XFmode);
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emit_insn (gen_extendsfxf2 (op1, operands[1]));
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emit_insn (gen_frndintxf2_trunc (op0, op1));
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emit_insn (gen_truncxfsf2_i387_noop (operands[0], op0));
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emit_insn (gen_truncxf<mode>2_i387_noop (operands[0], op0));
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}
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DONE;
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})
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@ -6338,7 +6338,7 @@
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[(set (match_operand:V2DF 0 "register_operand" "=x")
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(unspec:V2DF [(match_operand:V2DF 1 "nonimmediate_operand" "xm")
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(match_operand:SI 2 "const_0_to_15_operand" "n")]
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UNSPEC_ROUNDP))]
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UNSPEC_ROUND))]
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"TARGET_SSE4_1"
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"roundpd\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "ssecvt")
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@ -6349,7 +6349,7 @@
|
||||
[(set (match_operand:V4SF 0 "register_operand" "=x")
|
||||
(unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")
|
||||
(match_operand:SI 2 "const_0_to_15_operand" "n")]
|
||||
UNSPEC_ROUNDP))]
|
||||
UNSPEC_ROUND))]
|
||||
"TARGET_SSE4_1"
|
||||
"roundps\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "ssecvt")
|
||||
@ -6361,7 +6361,7 @@
|
||||
(vec_merge:V2DF
|
||||
(unspec:V2DF [(match_operand:V2DF 2 "register_operand" "x")
|
||||
(match_operand:SI 3 "const_0_to_15_operand" "n")]
|
||||
UNSPEC_ROUNDS)
|
||||
UNSPEC_ROUND)
|
||||
(match_operand:V2DF 1 "register_operand" "0")
|
||||
(const_int 1)))]
|
||||
"TARGET_SSE4_1"
|
||||
@ -6375,7 +6375,7 @@
|
||||
(vec_merge:V4SF
|
||||
(unspec:V4SF [(match_operand:V4SF 2 "register_operand" "x")
|
||||
(match_operand:SI 3 "const_0_to_15_operand" "n")]
|
||||
UNSPEC_ROUNDS)
|
||||
UNSPEC_ROUND)
|
||||
(match_operand:V4SF 1 "register_operand" "0")
|
||||
(const_int 1)))]
|
||||
"TARGET_SSE4_1"
|
||||
@ -6504,14 +6504,14 @@
|
||||
(match_operand:SI 3 "register_operand" "d,d,d,d")
|
||||
(match_operand:SI 4 "const_0_to_255_operand" "n,n,n,n")]
|
||||
UNSPEC_PCMPESTR))
|
||||
(clobber (match_scratch:SI 5 "=c,c,X,X"))
|
||||
(clobber (match_scratch:V16QI 6 "=X,X,Y0,Y0"))]
|
||||
(clobber (match_scratch:V16QI 5 "=Y0,Y0,X,X"))
|
||||
(clobber (match_scratch:SI 6 "= X, X,c,c"))]
|
||||
"TARGET_SSE4_2"
|
||||
"@
|
||||
pcmpestri\t{%4, %2, %0|%0, %2, %4}
|
||||
pcmpestri\t{%4, %2, %0|%0, %2, %4}
|
||||
pcmpestrm\t{%4, %2, %0|%0, %2, %4}
|
||||
pcmpestrm\t{%4, %2, %0|%0, %2, %4}"
|
||||
pcmpestrm\t{%4, %2, %0|%0, %2, %4}
|
||||
pcmpestri\t{%4, %2, %0|%0, %2, %4}
|
||||
pcmpestri\t{%4, %2, %0|%0, %2, %4}"
|
||||
[(set_attr "type" "sselog")
|
||||
(set_attr "prefix_data16" "1")
|
||||
(set_attr "prefix_extra" "1")
|
||||
@ -6613,14 +6613,14 @@
|
||||
(match_operand:V16QI 1 "nonimmediate_operand" "x,m,x,m")
|
||||
(match_operand:SI 2 "const_0_to_255_operand" "n,n,n,n")]
|
||||
UNSPEC_PCMPISTR))
|
||||
(clobber (match_scratch:SI 3 "=c,c,X,X"))
|
||||
(clobber (match_scratch:V16QI 4 "=X,X,Y0,Y0"))]
|
||||
(clobber (match_scratch:V16QI 3 "=Y0,Y0,X,X"))
|
||||
(clobber (match_scratch:SI 4 "= X, X,c,c"))]
|
||||
"TARGET_SSE4_2"
|
||||
"@
|
||||
pcmpistri\t{%2, %1, %0|%0, %1, %2}
|
||||
pcmpistri\t{%2, %1, %0|%0, %1, %2}
|
||||
pcmpistrm\t{%2, %1, %0|%0, %1, %2}
|
||||
pcmpistrm\t{%2, %1, %0|%0, %1, %2}"
|
||||
pcmpistrm\t{%2, %1, %0|%0, %1, %2}
|
||||
pcmpistri\t{%2, %1, %0|%0, %1, %2}
|
||||
pcmpistri\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "type" "sselog")
|
||||
(set_attr "prefix_data16" "1")
|
||||
(set_attr "prefix_extra" "1")
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user