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mcore-protos.h (mcore_r15_operand_p): Declare.
* config/mcore/mcore-protos.h (mcore_r15_operand_p): Declare.
(mcore_secondary_reload_class): Declare.
(mcore_output_inline_const_forced): Remove.
* config/mcore/mcore.md (movsi): Remove the code that forced
non-inlineable constants into a register if the target was r15
or the stack pointer. Remove constant restrictions from the main
define_insn. Remove r <- I, r <- M and r <- N alternatives in favor
of an r <- P alternative. Remove fallback define_insn for reload.
(movhi, movqi): Use gen_lowpart rather than gen_SUBREG. Remove reload
define_insn. Use mcore_output_move in the remaining define_insn.
Adjust condition and constraints in the way as for movsi.
(movdi): Always split unacceptable constants into two. Use
simplify_gen_subreg instead of operand_subword{,_force}.
* config/mcore/mcore.c (mcore_output_inline_const_forced): Remove.
(mcore_output_move): Support HImode and QImode moves as well.
(mcore_m15_operand_p): New function.
(mcore_reload_class): Use it to detect cases where LRW_REGS are better.
(mcore_secondary_reload_class): New function.
* config/mcore/mcore.h (SECONDARY_RELOAD_CLASS): Redefine in
terms of mcore_secondary_reload_class.
From-SVN: r71330
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
70b160738b
commit
f0f4da3220
@ -1,3 +1,26 @@
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2003-09-12 Richard Sandiford <rsandifo@redhat.com>
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* config/mcore/mcore-protos.h (mcore_r15_operand_p): Declare.
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(mcore_secondary_reload_class): Declare.
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(mcore_output_inline_const_forced): Remove.
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* config/mcore/mcore.md (movsi): Remove the code that forced
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non-inlineable constants into a register if the target was r15
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or the stack pointer. Remove constant restrictions from the main
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define_insn. Remove r <- I, r <- M and r <- N alternatives in favor
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of an r <- P alternative. Remove fallback define_insn for reload.
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(movhi, movqi): Use gen_lowpart rather than gen_SUBREG. Remove reload
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define_insn. Use mcore_output_move in the remaining define_insn.
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Adjust condition and constraints in the way as for movsi.
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(movdi): Always split unacceptable constants into two. Use
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simplify_gen_subreg instead of operand_subword{,_force}.
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* config/mcore/mcore.c (mcore_output_inline_const_forced): Remove.
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(mcore_output_move): Support HImode and QImode moves as well.
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(mcore_m15_operand_p): New function.
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(mcore_reload_class): Use it to detect cases where LRW_REGS are better.
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(mcore_secondary_reload_class): New function.
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* config/mcore/mcore.h (SECONDARY_RELOAD_CLASS): Redefine in
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terms of mcore_secondary_reload_class.
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2003-09-11 Mike Stump <mrs@apple.com>
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* c-lex.c (fe_file_change): Don't transform to_line with SOURCE_LINE.
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@ -65,6 +65,8 @@ extern void mcore_print_operand_address PARAMS ((FILE *, rtx));
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extern void mcore_print_operand PARAMS ((FILE *, rtx, int));
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extern rtx mcore_gen_compare_reg PARAMS ((RTX_CODE));
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extern int mcore_symbolic_address_p PARAMS ((rtx));
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extern bool mcore_r15_operand_p PARAMS ((rtx));
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extern enum reg_class mcore_secondary_reload_class PARAMS ((enum reg_class, enum machine_mode, rtx));
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extern enum reg_class mcore_reload_class PARAMS ((rtx, enum reg_class));
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extern int mcore_is_same_reg PARAMS ((rtx, rtx));
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extern int mcore_arith_S_operand PARAMS ((rtx));
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@ -72,7 +74,6 @@ extern int mcore_arith_S_operand PARAMS ((rtx));
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#ifdef HAVE_MACHINE_MODES
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extern const char * mcore_output_move PARAMS ((rtx, rtx *, enum machine_mode));
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extern const char * mcore_output_movedouble PARAMS ((rtx *, enum machine_mode));
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extern const char * mcore_output_inline_const_forced PARAMS ((rtx, rtx *, enum machine_mode));
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extern int mcore_arith_reg_operand PARAMS ((rtx, enum machine_mode));
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extern int mcore_general_movsrc_operand PARAMS ((rtx, enum machine_mode));
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extern int mcore_general_movdst_operand PARAMS ((rtx, enum machine_mode));
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@ -1270,7 +1270,17 @@ mcore_output_move (insn, operands, mode)
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if (GET_CODE (XEXP (src, 0)) == LABEL_REF)
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return "lrw\t%0,[%1]"; /* a-R */
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else
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return "ldw\t%0,%1"; /* r-m */
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switch (GET_MODE (src)) /* r-m */
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{
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case SImode:
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return "ldw\t%0,%1";
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case HImode:
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return "ld.h\t%0,%1";
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case QImode:
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return "ld.b\t%0,%1";
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default:
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abort ();
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}
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}
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else if (GET_CODE (src) == CONST_INT)
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{
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@ -1291,100 +1301,21 @@ mcore_output_move (insn, operands, mode)
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return "lrw\t%0, %1"; /* Into the literal pool. */
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}
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else if (GET_CODE (dst) == MEM) /* m-r */
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return "stw\t%1,%0";
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switch (GET_MODE (dst))
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{
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case SImode:
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return "stw\t%1,%0";
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case HImode:
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return "st.h\t%1,%0";
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case QImode:
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return "st.b\t%1,%0";
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default:
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abort ();
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}
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abort ();
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}
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/* Outputs a constant inline -- regardless of the cost.
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Useful for things where we've gotten into trouble and think we'd
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be doing an lrw into r15 (forbidden). This lets us get out of
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that pickle even after register allocation. */
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const char *
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mcore_output_inline_const_forced (insn, operands, mode)
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rtx insn ATTRIBUTE_UNUSED;
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rtx operands[];
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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unsigned long value = INTVAL (operands[1]);
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unsigned long ovalue = value;
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struct piece
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{
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int low;
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int shift;
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}
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part[6];
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int i;
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if (mcore_const_ok_for_inline (value))
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return output_inline_const (SImode, operands);
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for (i = 0; (unsigned) i < ARRAY_SIZE (part); i++)
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{
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part[i].shift = 0;
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part[i].low = (value & 0x1F);
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value -= part[i].low;
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if (mcore_const_ok_for_inline (value))
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break;
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else
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{
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value >>= 5;
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part[i].shift = 5;
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while ((value & 1) == 0)
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{
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part[i].shift++;
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value >>= 1;
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}
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if (mcore_const_ok_for_inline (value))
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break;
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}
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}
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/* 5 bits per iteration, a maximum of 5 times == 25 bits and leaves
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7 bits left in the constant -- which we know we can cover with
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a movi. The final value can't be zero otherwise we'd have stopped
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in the previous iteration. */
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if (value == 0 || ! mcore_const_ok_for_inline (value))
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abort ();
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/* Now, work our way backwards emitting the constant. */
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/* Emit the value that remains -- it will be nonzero. */
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operands[1] = GEN_INT (value);
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output_asm_insn (output_inline_const (SImode, operands), operands);
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while (i >= 0)
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{
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/* Shift anything we've already loaded. */
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if (part[i].shift)
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{
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operands[2] = GEN_INT (part[i].shift);
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output_asm_insn ("lsli %0,%2", operands);
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value <<= part[i].shift;
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}
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/* Add anything we need into the low 5 bits. */
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if (part[i].low != 0)
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{
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operands[2] = GEN_INT (part[i].low);
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output_asm_insn ("addi %0,%2", operands);
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value += part[i].low;
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}
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i--;
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}
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if (value != ovalue) /* sanity */
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abort ();
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/* We've output all the instructions. */
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return "";
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}
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/* Return a sequence of instructions to perform DI or DF move.
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Since the MCORE cannot move a DI or DF in one instruction, we have
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to take care when we see overlapping source and dest registers. */
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@ -3064,36 +2995,53 @@ mcore_reorg ()
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}
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/* Return true if X is something that can be moved directly into r15. */
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bool
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mcore_r15_operand_p (x)
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rtx x;
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{
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switch (GET_CODE (x))
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{
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case CONST_INT:
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return mcore_const_ok_for_inline (INTVAL (x));
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case REG:
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case SUBREG:
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case MEM:
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return 1;
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default:
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return 0;
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}
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}
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/* Implement SECONDARY_RELOAD_CLASS. If CLASS contains r15, and we can't
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directly move X into it, use r1-r14 as a temporary. */
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enum reg_class
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mcore_secondary_reload_class (class, mode, x)
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enum reg_class class;
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enum machine_mode mode ATTRIBUTE_UNUSED;
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rtx x;
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{
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if (TEST_HARD_REG_BIT (reg_class_contents[class], 15)
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&& !mcore_r15_operand_p (x))
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return LRW_REGS;
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return NO_REGS;
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}
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/* Return the reg_class to use when reloading the rtx X into the class
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CLASS. */
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/* If the input is (PLUS REG CONSTANT) representing a stack slot address,
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then we want to restrict the class to LRW_REGS since that ensures that
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will be able to safely load the constant.
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If the input is a constant that should be loaded with mvir1, then use
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ONLYR1_REGS.
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??? We don't handle the case where we have (PLUS REG CONSTANT) and
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the constant should be loaded with mvir1, because that can lead to cases
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where an instruction needs two ONLYR1_REGS reloads. */
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CLASS. If X is too complex to move directly into r15, prefer to
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use LRW_REGS instead. */
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enum reg_class
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mcore_reload_class (x, class)
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rtx x;
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enum reg_class class;
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{
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enum reg_class new_class;
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if (reg_class_subset_p (LRW_REGS, class) && !mcore_r15_operand_p (x))
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return LRW_REGS;
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if (class == GENERAL_REGS && CONSTANT_P (x)
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&& (GET_CODE (x) != CONST_INT
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|| ( ! CONST_OK_FOR_I (INTVAL (x))
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&& ! CONST_OK_FOR_M (INTVAL (x))
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&& ! CONST_OK_FOR_N (INTVAL (x)))))
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new_class = LRW_REGS;
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else
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new_class = class;
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return new_class;
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return class;
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}
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/* Tell me if a pair of reg/subreg rtx's actually refer to the same
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@ -603,7 +603,8 @@ extern const enum reg_class reg_class_from_letter[];
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/* Return the register class of a scratch register needed to copy IN into
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or out of a register in CLASS in MODE. If it can be done directly,
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NO_REGS is returned. */
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#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) NO_REGS
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#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
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mcore_secondary_reload_class (CLASS, MODE, X)
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/* Return the maximum number of consecutive registers
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needed to represent mode MODE in a register of class CLASS.
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@ -1226,101 +1226,20 @@
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{
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if (GET_CODE (operands[0]) == MEM)
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operands[1] = force_reg (SImode, operands[1]);
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else if (CONSTANT_P (operands[1])
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&& (GET_CODE (operands[1]) != CONST_INT
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|| ( ! CONST_OK_FOR_I (INTVAL (operands[1]))
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&& ! CONST_OK_FOR_M (INTVAL (operands[1]))
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&& ! CONST_OK_FOR_N (INTVAL (operands[1]))
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&& (! TARGET_HARDLIT ||
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! mcore_const_ok_for_inline (INTVAL (operands[1])))))
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&& ! reload_completed
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&& ! reload_in_progress
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&& GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
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&& (REGNO (operands[0]) == STACK_POINTER_REGNUM
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|| REGNO (operands[0]) == LK_REG))
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operands[1] = force_reg (SImode, operands[1]);
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}")
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;;; Must put a/i before r/r so that it will be preferred when the dest is
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;;; a hard register. Must put a/R before r/m.
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;;; DO WE NEED a/i ANYMORE?
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(define_insn ""
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[(set (match_operand:SI 0 "mcore_general_movdst_operand" "=r,r,r,a,r,r,a,r,m")
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(match_operand:SI 1 "mcore_general_movsrc_operand" "I,M,N,i,r,c,R,m,r"))]
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[(set (match_operand:SI 0 "mcore_general_movdst_operand" "=r,r,a,r,a,r,m")
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(match_operand:SI 1 "mcore_general_movsrc_operand" "r,P,i,c,R,m,r"))]
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"(register_operand (operands[0], SImode)
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|| register_operand (operands[1], SImode))
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&& ! (CONSTANT_P (operands[1])
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&& (GET_CODE (operands[1]) != CONST_INT
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|| ( ! CONST_OK_FOR_I (INTVAL (operands[1]))
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&& ! CONST_OK_FOR_M (INTVAL (operands[1]))
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&& ! CONST_OK_FOR_N (INTVAL (operands[1]))))
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&& GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
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&& (REGNO (operands[0]) == STACK_POINTER_REGNUM
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|| REGNO (operands[0]) == LK_REG))"
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|| register_operand (operands[1], SImode))"
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"* return mcore_output_move (insn, operands, SImode);"
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[(set_attr "type" "move,move,move,move,move,move,load,load,store")])
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[(set_attr "type" "move,move,move,move,load,load,store")])
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;; This is to work around a bug in reload.
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(match_operand:SI 1 "immediate_operand" "i"))]
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"((reload_in_progress || reload_completed)
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&& CONSTANT_P (operands[1])
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&& GET_CODE (operands[1]) == CONST_INT
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&& ! CONST_OK_FOR_I (INTVAL (operands[1]))
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&& ! CONST_OK_FOR_M (INTVAL (operands[1]))
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&& ! CONST_OK_FOR_N (INTVAL (operands[1]))
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&& GET_CODE (operands[0]) == REG
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&& REGNO (operands[0]) == LK_REG)"
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"* return mcore_output_inline_const_forced (insn, operands, SImode);"
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[(set_attr "type" "load")])
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;; (define_expand "reload_insi"
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;; [(parallel [(match_operand:SI 0 "register_operand" "=r")
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;; (match_operand:SI 1 "general_operand" "")
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;; (match_operand:DI 2 "register_operand" "=&r")])]
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;; ""
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;; "
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;; {
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;; if (CONSTANT_P (operands[1])
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;; && GET_CODE (operands[1]) == CONST_INT
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;; && ! CONST_OK_FOR_I (INTVAL (operands[1]))
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;; && ! CONST_OK_FOR_M (INTVAL (operands[1]))
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;; && ! CONST_OK_FOR_N (INTVAL (operands[1]))
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;; && GET_CODE (operands[0]) == REG
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;; && (REGNO (operands[0]) == STACK_POINTER_REGNUM
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;; || REGNO (operands[0]) == LK_REG))
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;; {
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;; rtx tmp;
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;;
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;; if ( REGNO (operands[2]) == REGNO (operands[0])
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;; || REGNO (operands[2]) == STACK_POINTER_REGNUM
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;; || REGNO (operands[2]) == LK_REG)
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;; tmp = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
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;; else
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;; tmp = gen_rtx_REG (SImode, REGNO (operands[2]));
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;;
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;; emit_insn (gen_movsi (tmp, operands[1]));
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;; emit_insn (gen_movsi (operands[0], tmp));
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;; DONE;
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;; }
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;; emit_insn (gen_movsi (operands[0], operands[1]));
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;; DONE;
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;; }"
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;; )
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;;
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;; HImode
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;;
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;;; ??? This isn't guaranteed to work. It should be more like the SImode
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;;; patterns.
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(define_expand "movhi"
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[(set (match_operand:HI 0 "general_operand" "")
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(match_operand:HI 1 "general_operand" ""))]
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@ -1338,73 +1257,17 @@
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{
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rtx reg = gen_reg_rtx (SImode);
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emit_insn (gen_movsi (reg, operands[1]));
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operands[1] = gen_rtx (SUBREG, HImode, reg, 0);
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operands[1] = gen_lowpart (HImode, reg);
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}
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}")
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(define_insn ""
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[(set (match_operand:HI 0 "mcore_general_movdst_operand" "=r,r,r,r,r,r,m")
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(match_operand:HI 1 "mcore_general_movsrc_operand" "r,I,M,N,c,m,r"))]
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[(set (match_operand:HI 0 "mcore_general_movdst_operand" "=r,r,a,r,r,m")
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(match_operand:HI 1 "mcore_general_movsrc_operand" "r,P,i,c,m,r"))]
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"(register_operand (operands[0], HImode)
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|| register_operand (operands[1], HImode))
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&& (GET_CODE (operands[1]) != CONST_INT
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|| CONST_OK_FOR_M (INTVAL (operands[1]))
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|| CONST_OK_FOR_N (INTVAL (operands[1]))
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|| CONST_OK_FOR_I (INTVAL (operands[1])))"
|
||||
"@
|
||||
mov %0,%1
|
||||
movi %0,%1
|
||||
bgeni %0,%P1
|
||||
bmaski %0,%N1
|
||||
mvc %0
|
||||
ld.h %0,%1
|
||||
st.h %1,%0"
|
||||
[(set_attr "type" "move,move,move,move,move,load,store")])
|
||||
|
||||
;; Like movhi, but the const_int source can't be synthesized in
|
||||
;; a single-instruction. Fall back to the same things that
|
||||
;; are done for movsi in such cases. Presumes that we can
|
||||
;; modify any parts of the register that we wish.
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:HI 0 "mcore_general_movdst_operand" "=r,a")
|
||||
(match_operand:HI 1 "const_int_operand" "P,i"))]
|
||||
"GET_CODE (operands[1]) == CONST_INT
|
||||
&& INTVAL (operands[1]) > 127 && INTVAL (operands[1]) < 65536"
|
||||
"*
|
||||
{
|
||||
if (GET_CODE (operands[0])== REG && REGNO (operands[0]) == 15
|
||||
&& !mcore_const_ok_for_inline (INTVAL (operands[1])))
|
||||
{
|
||||
/* mcore_output_move would generate lrw r15 -- a forbidden combo */
|
||||
return mcore_output_inline_const_forced (insn, operands, SImode);
|
||||
}
|
||||
else
|
||||
return mcore_output_move (insn, operands, SImode);
|
||||
}"
|
||||
[(set_attr "type" "move")])
|
||||
|
||||
|
||||
;; if we're still looking around for things to use, here's a last
|
||||
;; ditch effort that just calls the move. We only let this happen
|
||||
;; if we're in the reload pass.
|
||||
;;
|
||||
(define_insn ""
|
||||
[(set (match_operand:HI 0 "mcore_general_movdst_operand" "=r,a")
|
||||
(match_operand:HI 1 "const_int_operand" "P,i"))]
|
||||
"reload_in_progress || reload_completed"
|
||||
"*
|
||||
{
|
||||
if (GET_CODE (operands[0])== REG && REGNO (operands[0]) == 15
|
||||
&& !mcore_const_ok_for_inline (INTVAL (operands[1])))
|
||||
{
|
||||
/* mcore_output_move would generate lrw r15 -- a forbidden combo */
|
||||
return mcore_output_inline_const_forced (insn, operands, SImode);
|
||||
}
|
||||
else
|
||||
return mcore_output_move (insn, operands, HImode);
|
||||
}"
|
||||
[(set_attr "type" "move")])
|
||||
|| register_operand (operands[1], HImode))"
|
||||
"* return mcore_output_move (insn, operands, HImode);"
|
||||
[(set_attr "type" "move,move,move,move,load,store")])
|
||||
|
||||
;;
|
||||
;; QImode
|
||||
@ -1427,67 +1290,18 @@
|
||||
{
|
||||
rtx reg = gen_reg_rtx (SImode);
|
||||
emit_insn (gen_movsi (reg, operands[1]));
|
||||
operands[1] = gen_rtx (SUBREG, QImode, reg, 0);
|
||||
operands[1] = gen_lowpart (QImode, reg);
|
||||
}
|
||||
}")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:QI 0 "mcore_general_movdst_operand" "=r,r,r,r,r,r,m")
|
||||
(match_operand:QI 1 "mcore_general_movsrc_operand" "r,I,M,N,c,m,r"))]
|
||||
[(set (match_operand:QI 0 "mcore_general_movdst_operand" "=r,r,a,r,r,m")
|
||||
(match_operand:QI 1 "mcore_general_movsrc_operand" "r,P,i,c,m,r"))]
|
||||
"(register_operand (operands[0], QImode)
|
||||
|| register_operand (operands[1], QImode))
|
||||
&& (GET_CODE (operands[1]) != CONST_INT
|
||||
|| CONST_OK_FOR_M (INTVAL (operands[1]))
|
||||
|| CONST_OK_FOR_N (INTVAL (operands[1]))
|
||||
|| CONST_OK_FOR_I (INTVAL (operands[1])))"
|
||||
"@
|
||||
mov %0,%1
|
||||
movi %0,%1
|
||||
bgeni %0,%P1
|
||||
bmaski %0,%N1
|
||||
mvc %0
|
||||
ld.b %0,%1
|
||||
st.b %1,%0"
|
||||
[(set_attr "type" "move,move,move,move,move,load,store")])
|
||||
|| register_operand (operands[1], QImode))"
|
||||
"* return mcore_output_move (insn, operands, QImode);"
|
||||
[(set_attr "type" "move,move,move,move,load,store")])
|
||||
|
||||
;; cover the case where the constant is 128..255; this isn't handled
|
||||
;; in the above case. We could if we wanted to mess with adding a
|
||||
;; new constraint class like M,N,I.
|
||||
(define_insn ""
|
||||
[(set (match_operand:QI 0 "mcore_general_movdst_operand" "=r")
|
||||
(match_operand:QI 1 "const_int_operand" ""))]
|
||||
"GET_CODE (operands[1]) == CONST_INT
|
||||
&& INTVAL (operands[1]) > 127 && INTVAL (operands[1]) < 256"
|
||||
"*
|
||||
{
|
||||
/* have a constant in range 128..255; have to do 2 insns; we can
|
||||
* do this with a movi followed by a bseti
|
||||
*/
|
||||
operands[2] = GEN_INT (INTVAL (operands[1]) & 0x7f);
|
||||
return \"movi\\t%0,%2\;bseti\\t%0,7\";
|
||||
}"
|
||||
[(set_attr "type" "move")])
|
||||
|
||||
;; if we're still looking around for things to use, here's a last
|
||||
;; ditch effort that just calls the move. We only let this happen
|
||||
;; if we're in the reload pass.
|
||||
;;
|
||||
(define_insn ""
|
||||
[(set (match_operand:QI 0 "mcore_general_movdst_operand" "=r,a")
|
||||
(match_operand:QI 1 "const_int_operand" "P,i"))]
|
||||
"(reload_in_progress || reload_completed)"
|
||||
"*
|
||||
{
|
||||
if (GET_CODE (operands[0])== REG && REGNO (operands[0]) == 15
|
||||
&& ! mcore_const_ok_for_inline (INTVAL (operands[1])))
|
||||
{
|
||||
/* mcore_output_move would generate lrw r15 -- a forbidden combo */
|
||||
return mcore_output_inline_const_forced (insn, operands, SImode);
|
||||
}
|
||||
else
|
||||
return mcore_output_move (insn, operands, QImode);
|
||||
}"
|
||||
[(set_attr "type" "move")])
|
||||
|
||||
;; DImode
|
||||
|
||||
@ -1502,15 +1316,12 @@
|
||||
else if (GET_CODE (operands[1]) == CONST_INT
|
||||
&& ! CONST_OK_FOR_I (INTVAL (operands[1]))
|
||||
&& ! CONST_OK_FOR_M (INTVAL (operands[1]))
|
||||
&& ! CONST_OK_FOR_N (INTVAL (operands[1]))
|
||||
&& ! reload_completed
|
||||
&& ! reload_in_progress
|
||||
&& GET_CODE (operands[0]) == REG)
|
||||
&& ! CONST_OK_FOR_N (INTVAL (operands[1])))
|
||||
{
|
||||
emit_move_insn (operand_subword (operands[0], 0, 1, DImode),
|
||||
operand_subword_force (operands[1], 0, DImode));
|
||||
emit_move_insn (operand_subword (operands[0], 1, 1, DImode),
|
||||
operand_subword_force (operands[1], 1, DImode));
|
||||
int i;
|
||||
for (i = 0; i < UNITS_PER_WORD * 2; i += UNITS_PER_WORD)
|
||||
emit_move_insn (simplify_gen_subreg (SImode, operands[0], DImode, i),
|
||||
simplify_gen_subreg (SImode, operands[1], DImode, i));
|
||||
DONE;
|
||||
}
|
||||
}")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user