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re PR bootstrap/49104 (bootstrap failure on AMD K6-2 with illegal instruction (cmove) in stage2)
PR target/49104 * config/i386/cpuid.h (bit_MMXEXT): New define. libcpp/ChangeLog: 2011-05-22 Uros Bizjak <ubizjak@gmail.com> PR target/49104 * lex.c (init_vectorized_lexer): Do not set "minimum" when __3dNOW_A__ is defined. Check bit_MMXEXT and bit_CMOV to use search_line_mmx. From-SVN: r174032
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@ -1,3 +1,8 @@
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2011-05-22 Uros Bizjak <ubizjak@gmail.com>
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PR target/49104
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* config/i386/cpuid.h (bit_MMXEXT): New define.
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2011-05-22 Nick Clifton <nickc@redhat.com>
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* config/stormy16/stormy16.c (xstormy16_init_builtins): prevent
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@ -7,8 +12,7 @@
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2011-05-22 Ira Rosen <ira.rosen@linaro.org>
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PR tree-optimization/49087
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* tree-vect-loop.c (vect_is_slp_reduction): Fail if
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LHS has no uses.
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* tree-vect-loop.c (vect_is_slp_reduction): Fail if LHS has no uses.
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2011-05-21 Jason Merrill <jason@redhat.com>
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@ -45,8 +49,7 @@
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* opt-read.awk: New. Split out of optc-gen.awk and opth-gen.awk.
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* optc-gen.awk: Move common code to opt-read.awk.
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* opth-gen.awk: Likewise.
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* Makefile.in (options.c, s-options-h): Update to use
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opt-read.awk.
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* Makefile.in (options.c, s-options-h): Update to use opt-read.awk.
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2011-05-20 Nathan Froyd <froydnj@codesourcery.com>
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@ -57,6 +57,7 @@
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#define bit_TBM (1 << 21)
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/* %edx */
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#define bit_MMXEXT (1 << 22)
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#define bit_LM (1 << 29)
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#define bit_3DNOWP (1 << 30)
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#define bit_3DNOW (1 << 31)
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@ -1,3 +1,9 @@
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2011-05-22 Uros Bizjak <ubizjak@gmail.com>
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PR target/49104
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* lex.c (init_vectorized_lexer): Do not set "minimum" when __3dNOW_A__
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is defined. Check bit_MMXEXT and bit_CMOV to use search_line_mmx.
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2011-04-25 Jan Kratochvil <jan.kratochvil@redhat.com>
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* system.h (ENUM_BITFIELD): Remove.
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@ -294,7 +294,7 @@ static const char repl_chars[4][16] __attribute__((aligned(16))) = {
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/* A version of the fast scanner using MMX vectorized byte compare insns.
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This uses the PMOVMSKB instruction which was introduced with "MMX2",
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which was packaged into SSE1; it is also present in the AMD 3dNOW-A
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which was packaged into SSE1; it is also present in the AMD MMX
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extension. Mark the function as using "sse" so that we emit a real
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"emms" instruction, rather than the 3dNOW "femms" instruction. */
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@ -488,7 +488,7 @@ init_vectorized_lexer (void)
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minimum = 3;
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#elif defined(__SSE2__)
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minimum = 2;
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#elif defined(__SSE__) || defined(__3dNOW_A__)
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#elif defined(__SSE__)
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minimum = 1;
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#endif
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@ -505,7 +505,7 @@ init_vectorized_lexer (void)
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}
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else if (__get_cpuid (0x80000001, &dummy, &dummy, &dummy, &edx))
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{
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if (minimum == 1 || edx & bit_3DNOWP)
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if (minimum == 1 || (edx & (bit_MMXEXT | bit_CMOV)))
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impl = search_line_mmx;
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}
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