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re PR rtl-optimization/10876 (Segfault when compiling KDE 3.1.2)
PR optimization/10876 * config/sparc/sparc.h (CONST_OK_FOR_LETTER): Add new 'O' constraint for constant 4096. (CONST_DOUBLE_OK_FOR_LETTER_P): Likewise. * config/sparc/sparc.md (adddi3 expander): Canonicalize pattern. Do not transform into MINUS insn for constant 4096. (*adddi3_sp64 insn): Canonicalize pattern. Add new alternative for constant 4096 as third operand. (addsi3 expander): Remove. (*addsi3 insn): Rename into 'addsi3'. Canonicalize pattern. Add new alternative for constant 4096 as third operand. (subdi3 expander): Do not transform into PLUS insn for constant 4096. (*subdi3_sp64 insn): Add new alternative for constant 4096 as third operand. (subsi3 expander): Remove. (*subsi3 insn): Rename into 'subsi3'. Add new alternative for constant 4096 as third operand. * doc/md.texi (Machine Constraints): Document new 'O' constraint for the SPARC port. From-SVN: r67426
This commit is contained in:
Eric Botcazou
Eric Botcazou
parent
74764b8442
commit
ef0139b122
@ -1,3 +1,25 @@
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2003-06-04 Eric Botcazou <ebotcazou@libertysurf.fr>
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PR optimization/10876
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* config/sparc/sparc.h (CONST_OK_FOR_LETTER): Add
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new 'O' constraint for constant 4096.
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(CONST_DOUBLE_OK_FOR_LETTER_P): Likewise.
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* config/sparc/sparc.md (adddi3 expander): Canonicalize pattern.
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Do not transform into MINUS insn for constant 4096.
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(*adddi3_sp64 insn): Canonicalize pattern. Add new alternative
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for constant 4096 as third operand.
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(addsi3 expander): Remove.
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(*addsi3 insn): Rename into 'addsi3'. Canonicalize pattern. Add
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new alternative for constant 4096 as third operand.
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(subdi3 expander): Do not transform into PLUS insn for constant 4096.
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(*subdi3_sp64 insn): Add new alternative for constant 4096 as third
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operand.
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(subsi3 expander): Remove.
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(*subsi3 insn): Rename into 'subsi3'. Add new alternative for
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constant 4096 as third operand.
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* doc/md.texi (Machine Constraints): Document new 'O' constraint for
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the SPARC port.
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2003-06-03 Chris Demetriou <cgd@broadcom.com>
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* config/mips/t-linux64 (CRTSTUFF_T_CFLAGS_S): Define.
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@ -1381,7 +1381,8 @@ extern char leaf_reg_remap[];
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`K' is used for constants which can be loaded with a single sethi insn.
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`L' is used for the range of constants supported by the movcc insns.
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`M' is used for the range of constants supported by the movrcc insns.
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`N' is like K, but for constants wider than 32 bits. */
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`N' is like K, but for constants wider than 32 bits.
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`O' is used for the range which is just 4096. */
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#define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
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#define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
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@ -1405,6 +1406,7 @@ extern char leaf_reg_remap[];
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: (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
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: (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
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: (C) == 'N' ? SPARC_SETHI_P (VALUE) \
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: (C) == 'O' ? (VALUE) == 4096 \
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: 0)
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/* Similar, but for floating constants, and defining letters G and H.
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@ -1413,6 +1415,7 @@ extern char leaf_reg_remap[];
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#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
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((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \
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: (C) == 'H' ? arith_double_operand (VALUE, DImode) \
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: (C) == 'O' ? arith_double_4096_operand (VALUE, DImode) \
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: 0)
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/* Given an rtx X being reloaded into a reg required to be
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@ -4748,13 +4748,11 @@
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;;- arithmetic instructions
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(define_expand "adddi3"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
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(match_operand:DI 2 "arith_double_add_operand" "rHI")))]
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[(set (match_operand:DI 0 "register_operand" "")
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(plus:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:DI 2 "arith_double_add_operand" "")))]
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""
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{
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HOST_WIDE_INT i;
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if (! TARGET_ARCH64)
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{
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emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
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@ -4765,21 +4763,6 @@
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gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
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DONE;
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}
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if (arith_double_4096_operand(operands[2], DImode))
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{
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switch (GET_CODE (operands[1]))
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{
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case CONST_INT: i = INTVAL (operands[1]); break;
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case CONST_DOUBLE: i = CONST_DOUBLE_LOW (operands[1]); break;
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default:
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emit_insn (gen_rtx_SET (VOIDmode, operands[0],
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gen_rtx_MINUS (DImode, operands[1],
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GEN_INT(-4096))));
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DONE;
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}
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emit_insn (gen_movdi (operands[0], GEN_INT (i + 4096)));
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DONE;
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}
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})
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(define_insn_and_split "adddi3_insn_sp32"
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@ -4945,40 +4928,24 @@
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[(set_attr "length" "2")])
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(define_insn "*adddi3_sp64"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
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(match_operand:DI 2 "arith_double_operand" "rHI")))]
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(plus:DI (match_operand:DI 1 "register_operand" "%r,r")
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(match_operand:DI 2 "arith_double_add_operand" "rHI,O")))]
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"TARGET_ARCH64"
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"add\t%1, %2, %0")
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"@
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add\t%1, %2, %0
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sub\t%1, -%2, %0")
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(define_expand "addsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,d")
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(plus:SI (match_operand:SI 1 "arith_operand" "%r,d")
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(match_operand:SI 2 "arith_add_operand" "rI,d")))]
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""
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{
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if (arith_4096_operand(operands[2], SImode))
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{
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if (GET_CODE (operands[1]) == CONST_INT)
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emit_insn (gen_movsi (operands[0],
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GEN_INT (INTVAL (operands[1]) + 4096)));
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else
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emit_insn (gen_rtx_SET (VOIDmode, operands[0],
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gen_rtx_MINUS (SImode, operands[1],
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GEN_INT(-4096))));
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DONE;
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}
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})
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(define_insn "*addsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,d")
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(plus:SI (match_operand:SI 1 "arith_operand" "%r,d")
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(match_operand:SI 2 "arith_operand" "rI,d")))]
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(define_insn "addsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r,d")
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(plus:SI (match_operand:SI 1 "register_operand" "%r,r,d")
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(match_operand:SI 2 "arith_add_operand" "rI,O,d")))]
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""
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"@
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add\t%1, %2, %0
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sub\t%1, -%2, %0
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fpadd32s\t%1, %2, %0"
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[(set_attr "type" "*,fp")])
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[(set_attr "type" "*,*,fp")])
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(define_insn "*cmp_cc_plus"
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[(set (reg:CC_NOOV 100)
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@ -5021,9 +4988,9 @@
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[(set_attr "type" "compare")])
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(define_expand "subdi3"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(minus:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "arith_double_add_operand" "rHI")))]
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[(set (match_operand:DI 0 "register_operand" "")
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(minus:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:DI 2 "arith_double_add_operand" "")))]
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""
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{
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if (! TARGET_ARCH64)
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@ -5036,13 +5003,6 @@
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gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
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DONE;
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}
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if (arith_double_4096_operand(operands[2], DImode))
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{
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emit_insn (gen_rtx_SET (VOIDmode, operands[0],
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gen_rtx_PLUS (DImode, operands[1],
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GEN_INT(-4096))));
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DONE;
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}
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})
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(define_insn_and_split "*subdi3_sp32"
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@ -5124,36 +5084,24 @@
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[(set_attr "length" "2")])
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(define_insn "*subdi3_sp64"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(minus:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "arith_double_operand" "rHI")))]
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(minus:DI (match_operand:DI 1 "register_operand" "r,r")
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(match_operand:DI 2 "arith_double_add_operand" "rHI,O")))]
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"TARGET_ARCH64"
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"sub\t%1, %2, %0")
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"@
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sub\t%1, %2, %0
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add\t%1, -%2, %0")
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(define_expand "subsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,d")
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(minus:SI (match_operand:SI 1 "register_operand" "r,d")
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(match_operand:SI 2 "arith_add_operand" "rI,d")))]
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""
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{
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if (arith_4096_operand(operands[2], SImode))
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{
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emit_insn (gen_rtx_SET (VOIDmode, operands[0],
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gen_rtx_PLUS (SImode, operands[1],
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GEN_INT(-4096))));
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DONE;
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}
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})
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(define_insn "*subsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,d")
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(minus:SI (match_operand:SI 1 "register_operand" "r,d")
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(match_operand:SI 2 "arith_operand" "rI,d")))]
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(define_insn "subsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r,d")
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(minus:SI (match_operand:SI 1 "register_operand" "r,r,d")
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(match_operand:SI 2 "arith_add_operand" "rI,O,d")))]
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""
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"@
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sub\t%1, %2, %0
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add\t%1, -%2, %0
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fpsub32s\t%1, %2, %0"
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[(set_attr "type" "*,fp")])
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[(set_attr "type" "*,*,fp")])
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(define_insn "*cmp_minus_cc"
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[(set (reg:CC_NOOV 100)
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@ -2057,6 +2057,9 @@ Same as @samp{K}, except that it verifies that bits that are not in the
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lower 32-bit range are all zero. Must be used instead of @samp{K} for
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modes wider than @code{SImode}
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@item O
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The constant 4096
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@item G
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Floating-point zero
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@ -1,3 +1,8 @@
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2003-06-04 Eric Botcazou <ebotcazou@libertysurf.fr>
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* gcc.c-torture/compile/20030604-1.c: New test.
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* gcc.dg/sparc-constant-1.c: New test.
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2003-06-03 Glen Nakamura <glen@imodulo.com>
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* gcc.dg/20020525-1.c: Replace 0x5a5a5a5a with -1.
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18
gcc/testsuite/gcc.c-torture/compile/20030604-1.c
Normal file
18
gcc/testsuite/gcc.c-torture/compile/20030604-1.c
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@ -0,0 +1,18 @@
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/* PR optimization/10876 */
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/* Contributed by Christian Ehrhardt */
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/* Verify that the SPARC port doesn't emit
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(minus) (reg) (const_int) insns. */
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void f(void)
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{
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unsigned int butterfly, block, offset;
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double *Z;
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for (block = 0; block < 512; block += 512) {
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double T1re, T2re;
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offset = butterfly + block;
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T1re += T2re;
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T2re = Z[offset] + T1re;
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}
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}
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12
gcc/testsuite/gcc.dg/sparc-constant-1.c
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12
gcc/testsuite/gcc.dg/sparc-constant-1.c
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@ -0,0 +1,12 @@
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/* PR optimization/10876 */
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/* { dg-do compile { target sparc*-*-* } } */
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/* Verify that adding the constant 4096 is turned
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into substracting the constant -4096. */
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int foo(int a)
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{
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return a+4096;
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}
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/* { dg-final { scan-assembler "sub" } } */
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