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rs6000: Prefer VSX insns over VMX ones (part 1: perm and mrg)
There are various VSX insns that do the same job as (older) AltiVec insns, just with a wider range of possible registers. Many patterns for such insns have the "v" alternative before the "wa" alternative, which makes the output less readable than possible (since vs32 is v0, and most insns before or after this insn will be VSX as well). This changes the define_insns for the mrg and perm machine instructions to prefer the VSX form. No behaviour change. Only one testcase needed a little adjustment as well. 2020-05-29 Segher Boessenkool <segher@kernel.crashing.org> * config/rs6000/altivec.md (altivec_vmrghw_direct): Prefer VSX form. (altivec_vmrglw_direct): Ditto. (altivec_vperm_<mode>_direct): Ditto. (altivec_vperm_v8hiv16qi): Ditto. (*altivec_vperm_<mode>_uns_internal): Ditto. (*altivec_vpermr_<mode>_internal): Ditto. (vperm_v8hiv4si): Ditto. (vperm_v16qiv8hi): Ditto. gcc/testsuite/ * gcc.target/powerpc/vsx-vector-6.p9.c: Allow xxperm as perm as well.
This commit is contained in:
Segher Boessenkool
parent
c75ebe76ae
commit
ee969a36d9
@ -1216,14 +1216,14 @@
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[(set_attr "type" "vecperm")])
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(define_insn "altivec_vmrghw_direct"
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[(set (match_operand:V4SI 0 "register_operand" "=v,wa")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v,wa")
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(match_operand:V4SI 2 "register_operand" "v,wa")]
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[(set (match_operand:V4SI 0 "register_operand" "=wa,v")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "wa,v")
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(match_operand:V4SI 2 "register_operand" "wa,v")]
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UNSPEC_VMRGH_DIRECT))]
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"TARGET_ALTIVEC"
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"@
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vmrghw %0,%1,%2
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xxmrghw %x0,%x1,%x2"
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xxmrghw %x0,%x1,%x2
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vmrghw %0,%1,%2"
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[(set_attr "type" "vecperm")])
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(define_insn "*altivec_vmrghsf"
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@ -1364,14 +1364,14 @@
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[(set_attr "type" "vecperm")])
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(define_insn "altivec_vmrglw_direct"
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[(set (match_operand:V4SI 0 "register_operand" "=v,wa")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v,wa")
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(match_operand:V4SI 2 "register_operand" "v,wa")]
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[(set (match_operand:V4SI 0 "register_operand" "=wa,v")
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(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "wa,v")
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(match_operand:V4SI 2 "register_operand" "wa,v")]
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UNSPEC_VMRGL_DIRECT))]
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"TARGET_ALTIVEC"
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"@
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vmrglw %0,%1,%2
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xxmrglw %x0,%x1,%x2"
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xxmrglw %x0,%x1,%x2
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vmrglw %0,%1,%2"
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[(set_attr "type" "vecperm")])
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(define_insn "*altivec_vmrglsf"
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@ -2193,30 +2193,30 @@
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;; Slightly prefer vperm, since the target does not overlap the source
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(define_insn "altivec_vperm_<mode>_direct"
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[(set (match_operand:VM 0 "register_operand" "=v,?wa")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v,wa")
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(match_operand:VM 2 "register_operand" "v,0")
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(match_operand:V16QI 3 "register_operand" "v,wa")]
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[(set (match_operand:VM 0 "register_operand" "=?wa,v")
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(unspec:VM [(match_operand:VM 1 "register_operand" "wa,v")
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(match_operand:VM 2 "register_operand" "0,v")
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(match_operand:V16QI 3 "register_operand" "wa,v")]
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UNSPEC_VPERM))]
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"TARGET_ALTIVEC"
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"@
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vperm %0,%1,%2,%3
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xxperm %x0,%x1,%x3"
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xxperm %x0,%x1,%x3
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vperm %0,%1,%2,%3"
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[(set_attr "type" "vecperm")
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(set_attr "isa" "*,p9v")])
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(set_attr "isa" "p9v,*")])
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(define_insn "altivec_vperm_v8hiv16qi"
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[(set (match_operand:V16QI 0 "register_operand" "=v,?wa")
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(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v,wa")
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(match_operand:V8HI 2 "register_operand" "v,0")
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(match_operand:V16QI 3 "register_operand" "v,wa")]
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[(set (match_operand:V16QI 0 "register_operand" "=?wa,v")
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(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "wa,v")
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(match_operand:V8HI 2 "register_operand" "0,v")
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(match_operand:V16QI 3 "register_operand" "wa,v")]
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UNSPEC_VPERM))]
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"TARGET_ALTIVEC"
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"@
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vperm %0,%1,%2,%3
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xxperm %x0,%x1,%x3"
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xxperm %x0,%x1,%x3
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vperm %0,%1,%2,%3"
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[(set_attr "type" "vecperm")
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(set_attr "isa" "*,p9v")])
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(set_attr "isa" "p9v,*")])
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(define_expand "altivec_vperm_<mode>_uns"
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[(set (match_operand:VM 0 "register_operand")
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@ -2234,17 +2234,17 @@
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})
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(define_insn "*altivec_vperm_<mode>_uns_internal"
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[(set (match_operand:VM 0 "register_operand" "=v,?wa")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v,wa")
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(match_operand:VM 2 "register_operand" "v,0")
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(match_operand:V16QI 3 "register_operand" "v,wa")]
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[(set (match_operand:VM 0 "register_operand" "=?wa,v")
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(unspec:VM [(match_operand:VM 1 "register_operand" "wa,v")
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(match_operand:VM 2 "register_operand" "0,v")
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(match_operand:V16QI 3 "register_operand" "wa,v")]
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UNSPEC_VPERM_UNS))]
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"TARGET_ALTIVEC"
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"@
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vperm %0,%1,%2,%3
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xxperm %x0,%x1,%x3"
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xxperm %x0,%x1,%x3
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vperm %0,%1,%2,%3"
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[(set_attr "type" "vecperm")
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(set_attr "isa" "*,p9v")])
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(set_attr "isa" "p9v,*")])
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(define_expand "vec_permv16qi"
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[(set (match_operand:V16QI 0 "register_operand")
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@ -2261,17 +2261,17 @@
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})
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(define_insn "*altivec_vpermr_<mode>_internal"
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[(set (match_operand:VM 0 "register_operand" "=v,?wa")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v,wa")
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(match_operand:VM 2 "register_operand" "v,0")
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(match_operand:V16QI 3 "register_operand" "v,wa")]
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[(set (match_operand:VM 0 "register_operand" "=?wa,v")
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(unspec:VM [(match_operand:VM 1 "register_operand" "wa,v")
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(match_operand:VM 2 "register_operand" "0,v")
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(match_operand:V16QI 3 "register_operand" "wa,v")]
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UNSPEC_VPERMR))]
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"TARGET_P9_VECTOR"
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"@
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vpermr %0,%1,%2,%3
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xxpermr %x0,%x1,%x3"
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xxpermr %x0,%x1,%x3
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vpermr %0,%1,%2,%3"
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[(set_attr "type" "vecperm")
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(set_attr "isa" "*,p9v")])
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(set_attr "isa" "p9v,*")])
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(define_insn "altivec_vrfip" ; ceil
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[(set (match_operand:V4SF 0 "register_operand" "=v")
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@ -3414,30 +3414,30 @@
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"")
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(define_insn "vperm_v8hiv4si"
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[(set (match_operand:V4SI 0 "register_operand" "=v,?wa")
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(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v,wa")
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(match_operand:V4SI 2 "register_operand" "v,0")
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(match_operand:V16QI 3 "register_operand" "v,wa")]
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[(set (match_operand:V4SI 0 "register_operand" "=?wa,v")
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(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "wa,v")
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(match_operand:V4SI 2 "register_operand" "0,v")
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(match_operand:V16QI 3 "register_operand" "wa,v")]
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UNSPEC_VPERMSI))]
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"TARGET_ALTIVEC"
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"@
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vperm %0,%1,%2,%3
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xxperm %x0,%x1,%x3"
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xxperm %x0,%x1,%x3
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vperm %0,%1,%2,%3"
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[(set_attr "type" "vecperm")
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(set_attr "isa" "*,p9v")])
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(set_attr "isa" "p9v,*")])
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(define_insn "vperm_v16qiv8hi"
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[(set (match_operand:V8HI 0 "register_operand" "=v,?wa")
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(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v,wa")
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(match_operand:V8HI 2 "register_operand" "v,0")
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(match_operand:V16QI 3 "register_operand" "v,wa")]
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[(set (match_operand:V8HI 0 "register_operand" "=?wa,v")
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(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "wa,v")
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(match_operand:V8HI 2 "register_operand" "0,v")
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(match_operand:V16QI 3 "register_operand" "wa,v")]
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UNSPEC_VPERMHI))]
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"TARGET_ALTIVEC"
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"@
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vperm %0,%1,%2,%3
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xxperm %x0,%x1,%x3"
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xxperm %x0,%x1,%x3
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vperm %0,%1,%2,%3"
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[(set_attr "type" "vecperm")
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(set_attr "isa" "*,p9v")])
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(set_attr "isa" "p9v,*")])
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(define_insn "xxeval"
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[(set (match_operand:V2DI 0 "register_operand" "=wa")
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@ -9,7 +9,7 @@
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/* { dg-final { scan-assembler-times {\mvmaxub\M} 1 } } */
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/* { dg-final { scan-assembler-times {\mvmsumshs\M} 1 } } */
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/* { dg-final { scan-assembler-times {\mvmsumuhs\M} 1 } } */
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/* { dg-final { scan-assembler-times {\mvpermr?\M} 1 } } */
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/* { dg-final { scan-assembler-times {\m(?:vpermr?|xxperm)\M} 1 } } */
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/* { dg-final { scan-assembler-times {\mxvabsdp\M} 1 } } */
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/* { dg-final { scan-assembler-times {\mxvadddp\M} 1 } } */
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/* { dg-final { scan-assembler-times {\mxvcmpeqdp\M} 9 } } */
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