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[multiple changes]
2008-06-27 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/t-aix52: Append large data option to LDFLAGS for
genautomata.
2008-06-27 Edmar Wienskoski <edmar@freescale.com>
* config.gcc (powerpc*-*-*): Add new core e500mc.
* config/rs6000/e500mc.md: New file.
* config/rs6000/rs6000.c (processor_costs): Add new costs for
e500mc.
(rs6000_override_options): Add e500mc case to
processor_target_table. Altivec and Spe options not allowed
with e500mc. Add isel instruction to e500mc by
default. Initialize rs6000_cost for e500mc.
(rs6000_issue_rate): Set issue rate for e500mc.
* config/rs6000/rs6000.h (processor_type): Add
PROCESSOR_PPCE500MC.
(ASM_CPU_SPEC): Add e500mc.
Set TARGET_ISEL to rs6000_isel.
* config/rs6000/e500.h: Remove redefinition of TARGET_ISEL.
(CHECK_E500_OPTIONS): Remove TARGET_ISEL.
* config/rs6000/rs6000.md (define_attr "cpu"): Add ppce500mc..
Include e500mc.md.
* doc/invoke.texi: Add e500mc to list of cpus.
From-SVN: r137176
This commit is contained in:
David Edelsohn
parent
098b9c467c
commit
edae5fe3f2
@ -1,3 +1,29 @@
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2008-06-27 David Edelsohn <edelsohn@gnu.org>
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* config/rs6000/t-aix52: Append large data option to LDFLAGS for
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genautomata.
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2008-06-27 Edmar Wienskoski <edmar@freescale.com>
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* config.gcc (powerpc*-*-*): Add new core e500mc.
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* config/rs6000/e500mc.md: New file.
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* config/rs6000/rs6000.c (processor_costs): Add new costs for
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e500mc.
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(rs6000_override_options): Add e500mc case to
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processor_target_table. Altivec and Spe options not allowed
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with e500mc. Add isel instruction to e500mc by
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default. Initialize rs6000_cost for e500mc.
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(rs6000_issue_rate): Set issue rate for e500mc.
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* config/rs6000/rs6000.h (processor_type): Add
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PROCESSOR_PPCE500MC.
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(ASM_CPU_SPEC): Add e500mc.
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Set TARGET_ISEL to rs6000_isel.
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* config/rs6000/e500.h: Remove redefinition of TARGET_ISEL.
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(CHECK_E500_OPTIONS): Remove TARGET_ISEL.
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* config/rs6000/rs6000.md (define_attr "cpu"): Add ppce500mc.
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Include e500mc.md.
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* doc/invoke.texi: Add e500mc to list of cpus.
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2008-06-27 Laurynas Biveinis <laurynas.biveinis@gmail.com>
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PR c/34867
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@ -2819,8 +2819,9 @@ case "${target}" in
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| rios | rios1 | rios2 | rsc | rsc1 | rs64a \
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| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
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| 505 | 601 | 602 | 603 | 603e | ec603e | 604 \
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| 604e | 620 | 630 | 740 | 750 | 7400 | 7450 | e300c[23] \
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| 854[08] | 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
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| 604e | 620 | 630 | 740 | 750 | 7400 | 7450 \
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| e300c[23] | 854[08] | e500mc \
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| 801 | 821 | 823 | 860 | 970 | G3 | G4 | G5 | cell)
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# OK
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;;
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*)
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@ -19,7 +19,6 @@
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#undef TARGET_SPE_ABI
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#undef TARGET_SPE
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#undef TARGET_E500
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#undef TARGET_ISEL
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#undef TARGET_FPRS
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#undef TARGET_E500_SINGLE
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#undef TARGET_E500_DOUBLE
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@ -28,13 +27,12 @@
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#define TARGET_SPE_ABI rs6000_spe_abi
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#define TARGET_SPE rs6000_spe
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#define TARGET_E500 (rs6000_cpu == PROCESSOR_PPC8540)
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#define TARGET_ISEL rs6000_isel
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#define TARGET_FPRS (rs6000_float_gprs == 0)
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#define TARGET_E500_SINGLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 1)
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#define TARGET_E500_DOUBLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 2)
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#define CHECK_E500_OPTIONS \
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do { \
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if (TARGET_E500 || TARGET_SPE || TARGET_SPE_ABI || TARGET_ISEL \
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if (TARGET_E500 || TARGET_SPE || TARGET_SPE_ABI \
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|| TARGET_E500_SINGLE || TARGET_E500_DOUBLE) \
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{ \
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if (TARGET_ALTIVEC) \
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200
gcc/config/rs6000/e500mc.md
Normal file
200
gcc/config/rs6000/e500mc.md
Normal file
@ -0,0 +1,200 @@
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;; Pipeline description for Motorola PowerPC e500mc core.
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;; Copyright (C) 2008 Free Software Foundation, Inc.
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;; Contributed by Edmar Wienskoski (edmar@freescale.com)
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published
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;; by the Free Software Foundation; either version 3, or (at your
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;; option) any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but WITHOUT
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;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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;; License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;;
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;; e500mc 32-bit SU(2), LSU, FPU, BPU
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;; Max issue 3 insns/clock cycle (includes 1 branch)
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;; FP is half clocked, timings of other instructions are as in the e500v2.
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(define_automaton "e500mc_most,e500mc_long,e500mc_retire")
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(define_cpu_unit "e500mc_decode_0,e500mc_decode_1" "e500mc_most")
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(define_cpu_unit "e500mc_issue_0,e500mc_issue_1" "e500mc_most")
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(define_cpu_unit "e500mc_retire_0,e500mc_retire_1" "e500mc_retire")
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;; SU.
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(define_cpu_unit "e500mc_su0_stage0,e500mc_su1_stage0" "e500mc_most")
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;; MU.
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(define_cpu_unit "e500mc_mu_stage0,e500mc_mu_stage1" "e500mc_most")
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(define_cpu_unit "e500mc_mu_stage2,e500mc_mu_stage3" "e500mc_most")
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;; Non-pipelined division.
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(define_cpu_unit "e500mc_mu_div" "e500mc_long")
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;; LSU.
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(define_cpu_unit "e500mc_lsu" "e500mc_most")
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;; FPU.
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(define_cpu_unit "e500mc_fpu" "e500mc_most")
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;; Branch unit.
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(define_cpu_unit "e500mc_bu" "e500mc_most")
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;; The following units are used to make the automata deterministic.
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(define_cpu_unit "present_e500mc_decode_0" "e500mc_most")
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(define_cpu_unit "present_e500mc_issue_0" "e500mc_most")
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(define_cpu_unit "present_e500mc_retire_0" "e500mc_retire")
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(define_cpu_unit "present_e500mc_su0_stage0" "e500mc_most")
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;; The following sets to make automata deterministic when option ndfa is used.
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(presence_set "present_e500mc_decode_0" "e500mc_decode_0")
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(presence_set "present_e500mc_issue_0" "e500mc_issue_0")
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(presence_set "present_e500mc_retire_0" "e500mc_retire_0")
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(presence_set "present_e500mc_su0_stage0" "e500mc_su0_stage0")
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;; Some useful abbreviations.
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(define_reservation "e500mc_decode"
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"e500mc_decode_0|e500mc_decode_1+present_e500mc_decode_0")
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(define_reservation "e500mc_issue"
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"e500mc_issue_0|e500mc_issue_1+present_e500mc_issue_0")
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(define_reservation "e500mc_retire"
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"e500mc_retire_0|e500mc_retire_1+present_e500mc_retire_0")
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(define_reservation "e500mc_su_stage0"
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"e500mc_su0_stage0|e500mc_su1_stage0+present_e500mc_su0_stage0")
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;; Simple SU insns.
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(define_insn_reservation "e500mc_su" 1
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(and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\
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delayed_compare,var_delayed_compare,fast_compare,\
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shift,trap,var_shift_rotate,cntlz,exts")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
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(define_insn_reservation "e500mc_two" 1
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(and (eq_attr "type" "two")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
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e500mc_issue+e500mc_su_stage0+e500mc_retire")
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(define_insn_reservation "e500mc_three" 1
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(and (eq_attr "type" "three")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\
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e500mc_issue+e500mc_su_stage0+e500mc_retire,\
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e500mc_issue+e500mc_su_stage0+e500mc_retire")
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;; Multiply.
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(define_insn_reservation "e500mc_multiply" 4
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(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_mu_stage0,e500mc_mu_stage1,\
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e500mc_mu_stage2,e500mc_mu_stage3+e500mc_retire")
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;; Divide. We use the average latency time here.
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(define_insn_reservation "e500mc_divide" 14
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_mu_stage0+e500mc_mu_div,\
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e500mc_mu_div*13")
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;; Branch.
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(define_insn_reservation "e500mc_branch" 1
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(and (eq_attr "type" "jmpreg,branch,isync")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_bu,e500mc_retire")
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;; CR logical.
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(define_insn_reservation "e500mc_cr_logical" 1
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(and (eq_attr "type" "cr_logical,delayed_cr")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_bu,e500mc_retire")
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;; Mfcr.
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(define_insn_reservation "e500mc_mfcr" 1
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(and (eq_attr "type" "mfcr")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
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;; Mtcrf.
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(define_insn_reservation "e500mc_mtcrf" 1
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(and (eq_attr "type" "mtcr")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire")
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;; Mtjmpr.
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(define_insn_reservation "e500mc_mtjmpr" 1
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(and (eq_attr "type" "mtjmpr,mfjmpr")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
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;; Brinc.
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(define_insn_reservation "e500mc_brinc" 1
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(and (eq_attr "type" "brinc")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
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;; Loads.
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(define_insn_reservation "e500mc_load" 3
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(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
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load_l,sync")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
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(define_insn_reservation "e500mc_fpload" 4
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(and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_lsu,nothing*2,e500mc_retire")
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;; Stores.
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(define_insn_reservation "e500mc_store" 3
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(and (eq_attr "type" "store,store_ux,store_u,store_c")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
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(define_insn_reservation "e500mc_fpstore" 3
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(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire")
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;; The following ignores the retire unit to avoid a large automata.
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;; Simple FP.
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(define_insn_reservation "e500mc_simple_float" 8
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(and (eq_attr "type" "fpsimple")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_fpu")
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; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
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;; FP.
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(define_insn_reservation "e500mc_float" 8
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(and (eq_attr "type" "fp")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_fpu")
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; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire")
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(define_insn_reservation "e500mc_fpcompare" 8
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(and (eq_attr "type" "fpcompare")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_fpu")
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(define_insn_reservation "e500mc_dmul" 10
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(and (eq_attr "type" "dmul")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_fpu")
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;; FP divides are not pipelined.
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(define_insn_reservation "e500mc_sdiv" 36
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(and (eq_attr "type" "sdiv")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*35")
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(define_insn_reservation "e500mc_ddiv" 66
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(and (eq_attr "type" "ddiv")
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(eq_attr "cpu" "ppce500mc"))
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"e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*65")
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@ -694,6 +694,25 @@ struct processor_costs ppce300c2c3_cost = {
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1, /* prefetch streams /*/
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};
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/* Instruction costs on PPCE500MC processors. */
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static const
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struct processor_costs ppce500mc_cost = {
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COSTS_N_INSNS (4), /* mulsi */
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COSTS_N_INSNS (4), /* mulsi_const */
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COSTS_N_INSNS (4), /* mulsi_const9 */
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COSTS_N_INSNS (4), /* muldi */
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COSTS_N_INSNS (14), /* divsi */
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COSTS_N_INSNS (14), /* divdi */
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COSTS_N_INSNS (8), /* fp */
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COSTS_N_INSNS (10), /* dmul */
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COSTS_N_INSNS (36), /* sdiv */
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COSTS_N_INSNS (66), /* ddiv */
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64, /* cache line size */
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32, /* l1 cache */
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128, /* l2 cache */
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1, /* prefetch streams /*/
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};
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/* Instruction costs on POWER4 and POWER5 processors. */
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static const
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struct processor_costs power4_cost = {
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@ -1456,6 +1475,7 @@ rs6000_override_options (const char *default_cpu)
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{"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
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{"e300c2", PROCESSOR_PPCE300C2, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
|
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{"e300c3", PROCESSOR_PPCE300C3, POWERPC_BASE_MASK},
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{"e500mc", PROCESSOR_PPCE500MC, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
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{"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
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{"970", PROCESSOR_POWER4,
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POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
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@ -1559,10 +1579,12 @@ rs6000_override_options (const char *default_cpu)
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}
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}
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if (TARGET_E500 && !rs6000_explicit_options.isel)
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if ((TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC)
|
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&& !rs6000_explicit_options.isel)
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rs6000_isel = 1;
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if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3)
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if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
|
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|| rs6000_cpu == PROCESSOR_PPCE500MC)
|
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{
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if (TARGET_ALTIVEC)
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error ("AltiVec not supported in this target");
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@ -1679,9 +1701,9 @@ rs6000_override_options (const char *default_cpu)
|
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SUB3TARGET_OVERRIDE_OPTIONS;
|
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#endif
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if (TARGET_E500)
|
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if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC)
|
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{
|
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/* The e500 does not have string instructions, and we set
|
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/* The e500 and e500mc do not have string instructions, and we set
|
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MASK_STRING above when optimizing for size. */
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if ((target_flags & MASK_STRING) != 0)
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target_flags = target_flags & ~MASK_STRING;
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@ -1894,6 +1916,10 @@ rs6000_override_options (const char *default_cpu)
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rs6000_cost = &ppce300c2c3_cost;
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break;
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case PROCESSOR_PPCE500MC:
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rs6000_cost = &ppce500mc_cost;
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break;
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case PROCESSOR_POWER4:
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case PROCESSOR_POWER5:
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rs6000_cost = &power4_cost;
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@ -19008,6 +19034,7 @@ rs6000_issue_rate (void)
|
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case CPU_CELL:
|
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case CPU_PPCE300C2:
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case CPU_PPCE300C3:
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||||
case CPU_PPCE500MC:
|
||||
return 2;
|
||||
case CPU_RIOS2:
|
||||
case CPU_PPC604:
|
||||
|
||||
@ -133,6 +133,7 @@
|
||||
%{mcpu=8548: -me500} \
|
||||
%{mcpu=e300c2: -me300} \
|
||||
%{mcpu=e300c3: -me300} \
|
||||
%{mcpu=e500mc: -me500mc} \
|
||||
%{maltivec: -maltivec} \
|
||||
-many"
|
||||
|
||||
@ -282,6 +283,7 @@ enum processor_type
|
||||
PROCESSOR_PPC8540,
|
||||
PROCESSOR_PPCE300C2,
|
||||
PROCESSOR_PPCE300C3,
|
||||
PROCESSOR_PPCE500MC,
|
||||
PROCESSOR_POWER4,
|
||||
PROCESSOR_POWER5,
|
||||
PROCESSOR_POWER6,
|
||||
@ -400,7 +402,7 @@ extern enum rs6000_nop_insertion rs6000_sched_insert_nops;
|
||||
#define TARGET_SPE_ABI 0
|
||||
#define TARGET_SPE 0
|
||||
#define TARGET_E500 0
|
||||
#define TARGET_ISEL 0
|
||||
#define TARGET_ISEL rs6000_isel
|
||||
#define TARGET_FPRS 1
|
||||
#define TARGET_E500_SINGLE 0
|
||||
#define TARGET_E500_DOUBLE 0
|
||||
|
||||
@ -133,7 +133,7 @@
|
||||
;; Processor type -- this attribute must exactly match the processor_type
|
||||
;; enumeration in rs6000.h.
|
||||
|
||||
(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,power4,power5,power6,cell"
|
||||
(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,cell"
|
||||
(const (symbol_ref "rs6000_cpu_attr")))
|
||||
|
||||
|
||||
@ -167,6 +167,7 @@
|
||||
(include "7450.md")
|
||||
(include "8540.md")
|
||||
(include "e300c2c3.md")
|
||||
(include "e500mc.md")
|
||||
(include "power4.md")
|
||||
(include "power5.md")
|
||||
(include "power6.md")
|
||||
|
||||
@ -55,3 +55,5 @@ TARGET_LIBGCC2_CFLAGS = -mlong-double-128
|
||||
# Either 32-bit and 64-bit objects in archives.
|
||||
AR_FLAGS_FOR_TARGET = -X32_64
|
||||
|
||||
# genautomata requires more than 256MB of data
|
||||
build/genautomata : override LDFLAGS += -Wl,-bmaxdata:0x20000000
|
||||
|
||||
@ -13011,11 +13011,11 @@ Supported values for @var{cpu_type} are @samp{401}, @samp{403},
|
||||
@samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400},
|
||||
@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
|
||||
@samp{860}, @samp{970}, @samp{8540}, @samp{e300c2}, @samp{e300c3},
|
||||
@samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5}, @samp{power},
|
||||
@samp{power2}, @samp{power3}, @samp{power4}, @samp{power5},
|
||||
@samp{power5+}, @samp{power6}, @samp{power6x}, @samp{common},
|
||||
@samp{powerpc}, @samp{powerpc64}, @samp{rios}, @samp{rios1},
|
||||
@samp{rios2}, @samp{rsc}, and @samp{rs64}.
|
||||
@samp{e500mc}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
|
||||
@samp{power}, @samp{power2}, @samp{power3}, @samp{power4},
|
||||
@samp{power5}, @samp{power5+}, @samp{power6}, @samp{power6x},
|
||||
@samp{common}, @samp{powerpc}, @samp{powerpc64}, @samp{rios},
|
||||
@samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
|
||||
|
||||
@option{-mcpu=common} selects a completely generic processor. Code
|
||||
generated under this option will run on any POWER or PowerPC processor.
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user