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i386.c (IX86_BUILTIN_MOVQ, [...]): Remove.
* config/i386/i386.c (IX86_BUILTIN_MOVQ, IX86_BUILTIN_LOADD,
IX86_BUILTIN_STORED, IX86_BUILTIN_MOVQ2DQ,
IX86_BUILTIN_MOVDQ2Q): Remove.
(IX86_BUILTIN_VEC_EXT_V4SI): New.
(ix86_init_mmx_sse_builtins, ix86_expand_builtin): Update to match.
(ix86_expand_vector_extract): For V4S[FI], extract element 0 after
shuffling.
* config/i386/sse.md (sse_concatv2sf): Accept zero operand 2.
(sse2_pextrw): Fix immediate constraint.
(sse2_loadq, sse2_loadq_rex64): Remove.
* config/i386/emmintrin.h (_mm_cvtsi128_si32, _mm_cvtsi128_si64x):
Use __builtin_ia32_vec_ext_<size>.
(_mm_cvtsi32_si128, _mm_cvtsi64x_si128): Use _mm_set_epi<size>.
From-SVN: r93604
This commit is contained in:
Richard Henderson
Richard Henderson
parent
172847595a
commit
ed9b539671
@ -1,3 +1,19 @@
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2005-01-13 Richard Henderson <rth@redhat.com>
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* config/i386/i386.c (IX86_BUILTIN_MOVQ, IX86_BUILTIN_LOADD,
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IX86_BUILTIN_STORED, IX86_BUILTIN_MOVQ2DQ,
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IX86_BUILTIN_MOVDQ2Q): Remove.
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(IX86_BUILTIN_VEC_EXT_V4SI): New.
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(ix86_init_mmx_sse_builtins, ix86_expand_builtin): Update to match.
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(ix86_expand_vector_extract): For V4S[FI], extract element 0 after
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shuffling.
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* config/i386/sse.md (sse_concatv2sf): Accept zero operand 2.
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(sse2_pextrw): Fix immediate constraint.
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(sse2_loadq, sse2_loadq_rex64): Remove.
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* config/i386/emmintrin.h (_mm_cvtsi128_si32, _mm_cvtsi128_si64x):
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Use __builtin_ia32_vec_ext_<size>.
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(_mm_cvtsi32_si128, _mm_cvtsi64x_si128): Use _mm_set_epi<size>.
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2005-01-13 Aldy Hernandez <aldyh@redhat.com>
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* function.c (assign_parm_setup_block): Look inside original
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@ -195,20 +195,17 @@ _mm_storer_pd (double *__P, __m128d __A)
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static __inline int
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_mm_cvtsi128_si32 (__m128i __A)
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{
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int __tmp;
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__builtin_ia32_stored (&__tmp, (__v4si)__A);
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return __tmp;
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return __builtin_ia32_vec_ext_v4si ((__v4si)__A, 0);
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}
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#ifdef __x86_64__
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static __inline long long
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_mm_cvtsi128_si64x (__m128i __A)
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{
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return __builtin_ia32_movdq2q ((__v2di)__A);
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return __builtin_ia32_vec_ext_v2di ((__v2di)__A, 0);
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}
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#endif
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static __inline __m128d
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_mm_add_pd (__m128d __A, __m128d __B)
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{
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@ -1377,14 +1374,14 @@ _mm_mfence (void)
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static __inline __m128i
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_mm_cvtsi32_si128 (int __A)
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{
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return (__m128i) __builtin_ia32_loadd (&__A);
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return _mm_set_epi32 (0, 0, 0, __A);
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}
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#ifdef __x86_64__
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static __inline __m128i
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_mm_cvtsi64x_si128 (long long __A)
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{
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return (__m128i) __builtin_ia32_movq2dq (__A);
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return _mm_set_epi64x (0, __A);
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}
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#endif
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@ -12265,9 +12265,6 @@ enum ix86_builtins
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IX86_BUILTIN_LOADDQU,
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IX86_BUILTIN_STOREDQU,
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IX86_BUILTIN_MOVQ,
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IX86_BUILTIN_LOADD,
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IX86_BUILTIN_STORED,
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IX86_BUILTIN_PACKSSWB,
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IX86_BUILTIN_PACKSSDW,
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@ -12498,8 +12495,6 @@ enum ix86_builtins
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IX86_BUILTIN_MASKMOVDQU,
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IX86_BUILTIN_MOVMSKPD,
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IX86_BUILTIN_PMOVMSKB128,
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IX86_BUILTIN_MOVQ2DQ,
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IX86_BUILTIN_MOVDQ2Q,
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IX86_BUILTIN_PACKSSWB128,
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IX86_BUILTIN_PACKSSDW128,
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@ -12607,6 +12602,7 @@ enum ix86_builtins
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IX86_BUILTIN_VEC_EXT_V2DF,
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IX86_BUILTIN_VEC_EXT_V2DI,
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IX86_BUILTIN_VEC_EXT_V4SF,
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IX86_BUILTIN_VEC_EXT_V4SI,
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IX86_BUILTIN_VEC_EXT_V8HI,
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IX86_BUILTIN_VEC_EXT_V4HI,
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IX86_BUILTIN_VEC_SET_V8HI,
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@ -13154,8 +13150,6 @@ ix86_init_mmx_sse_builtins (void)
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= build_function_type_list (V2SI_type_node,
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V2SF_type_node, V2SF_type_node, NULL_TREE);
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tree pint_type_node = build_pointer_type (integer_type_node);
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tree pcint_type_node = build_pointer_type (
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build_type_variant (integer_type_node, 1, 0));
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tree pdouble_type_node = build_pointer_type (double_type_node);
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tree pcdouble_type_node = build_pointer_type (
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build_type_variant (double_type_node, 1, 0));
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@ -13168,12 +13162,6 @@ ix86_init_mmx_sse_builtins (void)
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intTI_type_node, intTI_type_node, NULL_TREE);
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tree void_ftype_pcvoid
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= build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
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tree v2di_ftype_di
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= build_function_type_list (V2DI_type_node,
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long_long_unsigned_type_node, NULL_TREE);
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tree di_ftype_v2di
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= build_function_type_list (long_long_unsigned_type_node,
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V2DI_type_node, NULL_TREE);
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tree v4sf_ftype_v4si
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= build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
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tree v4si_ftype_v4sf
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@ -13285,13 +13273,6 @@ ix86_init_mmx_sse_builtins (void)
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tree void_ftype_pchar_v16qi
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= build_function_type_list (void_type_node,
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pchar_type_node, V16QI_type_node, NULL_TREE);
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tree v4si_ftype_pcint
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= build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
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tree void_ftype_pcint_v4si
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= build_function_type_list (void_type_node,
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pcint_type_node, V4SI_type_node, NULL_TREE);
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tree v2di_ftype_v2di
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= build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
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tree float80_type;
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tree float128_type;
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@ -13479,8 +13460,6 @@ ix86_init_mmx_sse_builtins (void)
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/* SSE2 */
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def_builtin (MASK_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
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def_builtin (MASK_SSE2, "__builtin_ia32_movq2dq", v2di_ftype_di, IX86_BUILTIN_MOVQ2DQ);
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def_builtin (MASK_SSE2, "__builtin_ia32_movdq2q", di_ftype_v2di, IX86_BUILTIN_MOVDQ2Q);
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def_builtin (MASK_SSE2, "__builtin_ia32_loadupd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADUPD);
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def_builtin (MASK_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD);
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@ -13534,10 +13513,7 @@ ix86_init_mmx_sse_builtins (void)
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def_builtin (MASK_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
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def_builtin (MASK_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU);
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def_builtin (MASK_SSE2, "__builtin_ia32_loadd", v4si_ftype_pcint, IX86_BUILTIN_LOADD);
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def_builtin (MASK_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU);
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def_builtin (MASK_SSE2, "__builtin_ia32_stored", void_ftype_pcint_v4si, IX86_BUILTIN_STORED);
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def_builtin (MASK_SSE2, "__builtin_ia32_movq", v2di_ftype_v2di, IX86_BUILTIN_MOVQ);
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def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq", di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ);
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def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128);
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@ -13622,6 +13598,11 @@ ix86_init_mmx_sse_builtins (void)
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def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4sf",
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ftype, IX86_BUILTIN_VEC_EXT_V4SF);
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ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
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integer_type_node, NULL_TREE);
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def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4si",
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ftype, IX86_BUILTIN_VEC_EXT_V4SI);
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ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
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integer_type_node, NULL_TREE);
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def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v8hi",
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@ -14399,13 +14380,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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case IX86_BUILTIN_LOADDQU:
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return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu, arglist, target, 1);
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case IX86_BUILTIN_LOADD:
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return ix86_expand_unop_builtin (CODE_FOR_sse2_loadd, arglist, target, 1);
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case IX86_BUILTIN_STOREDQU:
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return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu, arglist);
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case IX86_BUILTIN_STORED:
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return ix86_expand_store_builtin (CODE_FOR_sse2_stored, arglist);
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case IX86_BUILTIN_MONITOR:
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arg0 = TREE_VALUE (arglist);
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@ -14447,6 +14423,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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case IX86_BUILTIN_VEC_EXT_V2DF:
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case IX86_BUILTIN_VEC_EXT_V2DI:
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case IX86_BUILTIN_VEC_EXT_V4SF:
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case IX86_BUILTIN_VEC_EXT_V4SI:
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case IX86_BUILTIN_VEC_EXT_V8HI:
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case IX86_BUILTIN_VEC_EXT_V4HI:
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return ix86_expand_vec_ext_builtin (arglist, target);
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@ -14480,8 +14457,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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if (d->code == fcode)
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return ix86_expand_sse_comi (d, arglist, target);
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/* @@@ Should really do something sensible here. */
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return 0;
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gcc_unreachable ();
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}
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/* Store OPERAND to the memory after reload is completed. This means
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@ -16402,6 +16378,7 @@ ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
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}
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vec = tmp;
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use_vec_extr = true;
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elt = 0;
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break;
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case V4SImode:
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@ -16431,6 +16408,7 @@ ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
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}
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vec = tmp;
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use_vec_extr = true;
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elt = 0;
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}
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else
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{
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@ -1067,16 +1067,18 @@
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;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE
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;; alternatives pretty much forces the MMX alternative to be chosen.
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(define_insn "*sse_concatv2sf"
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[(set (match_operand:V2SF 0 "register_operand" "=x,*y")
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[(set (match_operand:V2SF 0 "register_operand" "=x,x,*y,*y")
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(vec_concat:V2SF
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(match_operand:SF 1 "register_operand" " 0, 0")
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(match_operand:SF 2 "register_operand" " x,*y")))]
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(match_operand:SF 1 "nonimmediate_operand" " 0,m, 0, m")
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(match_operand:SF 2 "vector_move_operand" " x,C,*y, C")))]
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"TARGET_SSE"
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"@
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unpcklps\t{%2, %0|%0, %2}
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punpckldq\t{%2, %0|%0, %2}"
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[(set_attr "type" "sselog,mmxcvt")
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(set_attr "mode" "V4SF,DI")])
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movss\t{%1, %0|%0, %1}
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punpckldq\t{%2, %0|%0, %2}
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movd\t{%1, %0|%0, %1}"
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[(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
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(set_attr "mode" "V4SF,SF,DI,DI")])
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(define_insn "*sse_concatv4sf"
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[(set (match_operand:V4SF 0 "register_operand" "=x,x")
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@ -2671,7 +2673,7 @@
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(zero_extend:SI
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(vec_select:HI
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(match_operand:V8HI 1 "register_operand" "x")
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(parallel [(match_operand:SI 2 "const_0_to_7_operand" "0")]))))]
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(parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")]))))]
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"TARGET_SSE2"
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"pextrw\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "sselog")
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@ -2865,48 +2867,6 @@
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operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));
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})
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(define_expand "sse2_loadq"
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[(set (match_operand:V2DI 0 "register_operand" "")
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(vec_merge:V2DI
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(vec_duplicate:V2DI
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(match_operand:DI 1 "nonimmediate_operand" ""))
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(match_dup 2)
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(const_int 1)))]
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"TARGET_SSE"
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"operands[2] = CONST0_RTX (V2DImode);")
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(define_insn "*sse2_loadq"
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[(set (match_operand:V2DI 0 "register_operand" "=Y,?Y,Y,x")
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(vec_merge:V2DI
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(vec_duplicate:V2DI
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(match_operand:DI 1 "nonimmediate_operand" " m,*y,Y,0"))
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(match_operand:V2DI 2 "vector_move_operand" " C, C,0,x")
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(const_int 1)))]
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"TARGET_SSE && !TARGET_64BIT"
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"@
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movq\t{%1, %0|%0, %1}
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movq2dq\t{%1, %0|%0, %1}
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movq\t{%1, %0|%0, %1}
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shufps\t{$0xe4, %1, %0|%0, %1, 0xe4}"
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[(set_attr "type" "ssemov,ssemov,ssemov,sselog")
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(set_attr "mode" "TI,TI,TI,V4SF")])
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(define_insn "*sse2_loadq_rex64"
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[(set (match_operand:V2DI 0 "register_operand" "=x,?x,?x,x")
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(vec_merge:V2DI
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(vec_duplicate:V2DI
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(match_operand:DI 1 "nonimmediate_operand" " m,*y, r,x"))
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(match_operand:V2DI 2 "vector_move_operand" " C, C, C,0")
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(const_int 1)))]
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"TARGET_SSE2 && TARGET_64BIT"
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"@
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movq\t{%1, %0|%0, %1}
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movq2dq\t{%1, %0|%0, %1}
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movd\t{%1, %0|%0, %1}
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movq\t{%1, %0|%0, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "mode" "TI")])
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(define_insn "*vec_dupv4si"
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[(set (match_operand:V4SI 0 "register_operand" "=Y,x")
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(vec_duplicate:V4SI
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