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Fix vextract* masked patterns [PR93069]

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The AVX512F documentation clearly states that in instructions where the
destination is a memory only merging-masking is possible, not zero-masking,
and the assembler enforces that.

The testcase in this patch fails to assemble because of
Error: unsupported masking for `vextracti32x8'
on
        vextracti32x8   $0x0, %zmm1, -64(%rsp){%k1}{z}
For the vector extraction patterns, we apparently have 7 *_maskm patterns
that only accept memory destinations and rtx_equal_p merge-masking source
for it, 7 *<mask_name> corresponding patterns that allow memory destination
only for the non-masked cases (through <store_mask_constraint>), then 2
*<mask_name> patterns (lo ssehalf V16FI and lo ssehalf VI8F_256 ones) which
do allow memory destination even for masked cases and are the cause of the
testsuite failure, because we must not allow C constraint if the destination
is m, and finally one pair of patterns (separate * and *_mask, hi ssehalf
VI4F_256), which has another issue (for which I don't have a testcase
though), where if it would match zero-masking with register destination,
it wouldn't emit the needed {z} into assembly.
The attached patch fixes those 3 issues only, perhaps more suitable for
backporting.

2020-03-30  Jakub Jelinek  <jakub@redhat.com>

	PR target/93069
	* config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
	<store_mask_constraint> instead of m in output operand constraint.
	(vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
	%{%3%}.

	* gcc.target/i386/avx512vl-pr93069.c: New test.
	* gcc.dg/vect/pr93069.c: New test.
This commit is contained in:
Jakub Jelinek 2020-03-30 17:38:21 +02:00
parent 07c48b61a0
commit ec919cfcef
5 changed files with 41 additions and 3 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2020-03-30 Jakub Jelinek <jakub@redhat.com>
PR target/93069
* config/i386/sse.md (vec_extract_lo_<mode><mask_name>): Use
<store_mask_constraint> instead of m in output operand constraint.
(vec_extract_hi_<mode><mask_name>): Use <mask_operand2> instead of
%{%3%}.
2020-03-30 Alan Modra <amodra@gmail.com>
* config/rs6000/rs6000.c (rs6000_call_aix): Emit cookie to pattern.

8
gcc/config/i386/sse.md
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@ -8693,7 +8693,8 @@
})
(define_insn "vec_extract_lo_<mode><mask_name>"
[(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,v,m")
[(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
"=v,v,<store_mask_constraint>")
(vec_select:<ssehalfvecmode>
(match_operand:V16FI 1 "<store_mask_predicate>"
"v,<store_mask_constraint>,v")
@ -8750,7 +8751,8 @@
})
(define_insn "vec_extract_lo_<mode><mask_name>"
[(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,v,m")
[(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
"=v,v,<store_mask_constraint>")
(vec_select:<ssehalfvecmode>
(match_operand:VI8F_256 1 "<store_mask_predicate>"
"v,<store_mask_constraint>,v")
@ -8760,7 +8762,7 @@
&& (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
{
if (<mask_applied>)
return "vextract<shuffletype>64x2\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1, 0x0}";
return "vextract<shuffletype>64x2\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
else
return "#";
}

6
gcc/testsuite/ChangeLog
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@ -1,3 +1,9 @@
2020-03-30 Jakub Jelinek <jakub@redhat.com>
PR target/93069
* gcc.target/i386/avx512vl-pr93069.c: New test.
* gcc.dg/vect/pr93069.c: New test.
2020-03-29 Iain Buclaw <ibuclaw@gdcproject.org>
* lib/gdc-utils.exp: (gdc-convert-args): Handle compilation test

10
gcc/testsuite/gcc.dg/vect/pr93069.c Normal file
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@ -0,0 +1,10 @@
/* PR target/93069 */
/* { dg-do assemble { target vect_simd_clones } } */
/* { dg-options "-O2 -fopenmp-simd" } */
#pragma omp declare simd
int
foo (int x, int y)
{
return x == 0 ? x : y;
}

12
gcc/testsuite/gcc.target/i386/avx512vl-pr93069.c Normal file
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@ -0,0 +1,12 @@
/* PR target/93069 */
/* { dg-do assemble { target vect_simd_clones } } */
/* { dg-options "-O2 -fopenmp-simd -mtune=skylake-avx512" } */
/* { dg-additional-options "-mavx512vl" { target avx512vl } } */
/* { dg-additional-options "-mavx512dq" { target avx512dq } } */
#pragma omp declare simd
int
foo (int x, int y)
{
return x == 0 ? x : y;
}