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rs6000-power2-1.c: Change the options to be more correct.

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2004-04-29  Andrew Pinski  <pinskia@physics.uc.edu>

        * gcc.dg/rs6000-power2-1.c: Change the options to be more correct.
        * gcc.dg/rs6000-power2-2.c: Change the options to be more correct.
        Change the asm registers to be in form of frN instead of fN.

From-SVN: r81303
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Andrew Pinski 2004-04-29 20:23:36 +00:00 committed by Andrew Pinski
parent 15a6f2c33e
commit ec52e7d58f
3 changed files with 11 additions and 5 deletions
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6
gcc/testsuite/ChangeLog
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@ -1,3 +1,9 @@
2004-04-29 Andrew Pinski <pinskia@physics.uc.edu>
* gcc.dg/rs6000-power2-1.c: Change the options to be more correct.
* gcc.dg/rs6000-power2-2.c: Change the options to be more correct.
Change the asm registers to be in form of frN instead of fN.
2004-04-28 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* gcc.dg/torture/builtin-convert-2.c: New test.

2
gcc/testsuite/gcc.dg/rs6000-power2-1.c
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@ -1,5 +1,5 @@
/* { dg-do assemble { target powerpc-*-* rs6000-*-* } } */
/* { dg-options "-O -mpower2 -fno-schedule-insns -w" } */
/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */
/* This used to ICE as the peephole was not checking to see
if the register is a floating point one (I think this cannot
happen in real life except in this example). */

8
gcc/testsuite/gcc.dg/rs6000-power2-2.c
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@ -1,13 +1,13 @@
/* { dg-do assemble { target powerpc-*-* rs6000-*-* } } */
/* { dg-options "-O -mpower2 -fno-schedule-insns" } */
/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */
/* { dg-final { scan-assembler-not "lfd" } } */
/* { dg-final { scan-assembler-not "sfd" } } */
/* { dg-final { scan-assembler "lfq" } } */
/* { dg-final { scan-assembler "sfq" } } */
register double t1 __asm__("f0");
register double t2 __asm__("f1");
register double t3 __asm__("f2"), t4 __asm__("f3");
register double t1 __asm__("fr0");
register double t2 __asm__("fr1");
register double t3 __asm__("fr2"), t4 __asm__("fr3");
void t(double *a, double *b)
{
t1 = a[-1];