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[1/3][aarch64] Add vec_widen patterns to aarch64

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Add widening add and subtract patterns to the aarch64
backend. These allow taking vectors of N elements of size S
and performing and add/subtract on the high or low half
widening the resulting elements and storing N/2 elements of size 2*S.
These correspond to the addl,addl2,subl,subl2 instructions.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md: New patterns
	vec_widen_saddl_lo/hi_<mode>.
This commit is contained in:
Joel Hutton 2020-11-19 10:28:38 +00:00
parent ec383f0bdb
commit ec46904edf
1 changed files with 47 additions and 0 deletions

47
gcc/config/aarch64/aarch64-simd.md

@ -3382,6 +3382,53 @@
[(set_attr "type" "neon_<ADDSUB:optab>_long")]
)
(define_expand "vec_widen_<su>addl_lo_<mode>"
[(match_operand:<VWIDE> 0 "register_operand")
(ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))
(ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
emit_insn (gen_aarch64_<su>addl<mode>_lo_internal (operands[0], operands[1],
operands[2], p));
DONE;
})
(define_expand "vec_widen_<su>addl_hi_<mode>"
[(match_operand:<VWIDE> 0 "register_operand")
(ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))
(ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
emit_insn (gen_aarch64_<su>addl<mode>_hi_internal (operands[0], operands[1],
operands[2], p));
DONE;
})
(define_expand "vec_widen_<su>subl_lo_<mode>"
[(match_operand:<VWIDE> 0 "register_operand")
(ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))
(ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
emit_insn (gen_aarch64_<su>subl<mode>_lo_internal (operands[0], operands[1],
operands[2], p));
DONE;
})
(define_expand "vec_widen_<su>subl_hi_<mode>"
[(match_operand:<VWIDE> 0 "register_operand")
(ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))
(ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))]
"TARGET_SIMD"
{
rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
emit_insn (gen_aarch64_<su>subl<mode>_hi_internal (operands[0], operands[1],
operands[2], p));
DONE;
})
(define_expand "aarch64_saddl2<mode>"
[(match_operand:<VWIDE> 0 "register_operand")