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re PR c/11369 (too relaxed checking with -Wstrict-prototypes)
PR target/11369 * i386.c (ix86_expand_carry_flag_compare): Validate operand. PR target/11031 * i386.c (const_0_to_3_operand, const_0_to_7_operand, const_0_to_15_operand, const_0_to_255_operand): New predicates. * i386.h (PREDICATE_CODES): Add these. * i386.c (pinsrw and pextrw patterns): Use them. PR target/10984 * i386.c (ix86_expand_binop_builtin): Behave sanely for VOIDmodes. PR target/8869 * expr.c (convert_modes): Deal properly with integer to vector constant conversion. PR target/8871 * i386.md (zero_extendsidi2*): Add MMX and SSE alternatives. From-SVN: r70751
This commit is contained in:
Jan Hubicka
Jan Hubicka
parent
066ec9c97b
commit
ebe75517d4
@ -1,3 +1,24 @@
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Wed Aug 20 12:08:55 CEST 2003 Jan Hubicka <jh@suse.cz>
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PR target/11369
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* i386.c (ix86_expand_carry_flag_compare): Validate operand.
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PR target/11031
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* i386.c (const_0_to_3_operand, const_0_to_7_operand,
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const_0_to_15_operand, const_0_to_255_operand): New predicates.
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* i386.h (PREDICATE_CODES): Add these.
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* i386.c (pinsrw and pextrw patterns): Use them.
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PR target/10984
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* i386.c (ix86_expand_binop_builtin): Behave sanely for VOIDmodes.
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PR target/8869
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* expr.c (convert_modes): Deal properly with integer to vector
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constant conversion.
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PR target/8871
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* i386.md (zero_extendsidi2*): Add MMX and SSE alternatives.
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2003-08-23 Ulrich Weigand <uweigand@de.ibm.com>
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* config/s390/s390.h (LOAD_EXTEND_OP): Remove.
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@ -3596,6 +3596,32 @@ const248_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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&& (INTVAL (op) == 2 || INTVAL (op) == 4 || INTVAL (op) == 8));
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}
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int
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const_0_to_3_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 4);
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}
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int
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const_0_to_7_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 8);
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}
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int
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const_0_to_15_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 16);
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}
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int
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const_0_to_255_operand (register rtx op,
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enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 256);
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}
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/* True if this is a constant appropriate for an increment or decrement. */
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int
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@ -9400,11 +9426,6 @@ ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
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return false;
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code = (code == GTU ? GEU : LTU);
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}
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else if (!nonimmediate_operand (op1, mode)
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|| !general_operand (op0, mode))
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/* Swapping operands in this case would generate an
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unrecognizable insn. */
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return false;
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else
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{
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rtx tmp = op1;
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@ -9433,6 +9454,13 @@ ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
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default:
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return false;
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}
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/* Swapping operands may cause constant to appear as first operand. */
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if (!nonimmediate_operand (op0, VOIDmode))
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{
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if (no_new_pseudos)
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return false;
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op0 = force_reg (mode, op0);
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}
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ix86_compare_op0 = op0;
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ix86_compare_op1 = op1;
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*pop = ix86_expand_compare (code, NULL, NULL);
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@ -13508,7 +13536,8 @@ ix86_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
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/* In case the insn wants input operands in modes different from
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the result, abort. */
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if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
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if ((GET_MODE (op0) != mode0 && GET_MODE (op0) != VOIDmode)
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|| (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode))
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abort ();
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if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
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@ -13773,8 +13802,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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op0 = copy_to_mode_reg (mode0, op0);
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if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
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{
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/* @@@ better error message */
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error ("selector must be an immediate");
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error ("selector must be an integer constant in the range 0..%i",
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fcode == IX86_BUILTIN_PEXTRW ? 3:7);
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return gen_reg_rtx (tmode);
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}
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if (target == 0
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@ -13809,8 +13838,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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op1 = copy_to_mode_reg (mode1, op1);
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if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
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{
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/* @@@ better error message */
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error ("selector must be an immediate");
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error ("selector must be an integer constant in the range 0..%i",
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fcode == IX86_BUILTIN_PINSRW ? 15:255);
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return const0_rtx;
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}
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if (target == 0
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@ -3018,6 +3018,10 @@ do { \
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{"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
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{"const1_operand", {CONST_INT}}, \
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{"const248_operand", {CONST_INT}}, \
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{"const_0_to_3_operand", {CONST_INT}}, \
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{"const_0_to_7_operand", {CONST_INT}}, \
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{"const_0_to_15_operand", {CONST_INT}}, \
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{"const_0_to_255_operand", {CONST_INT}}, \
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{"incdec_operand", {CONST_INT}}, \
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{"mmx_reg_operand", {REG}}, \
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{"reg_no_sp_operand", {SUBREG, REG}}, \
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@ -3278,22 +3278,56 @@
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")
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(define_insn "zero_extendsidi2_32"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
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(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
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(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,m,m")))
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(clobber (reg:CC 17))]
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"!TARGET_64BIT"
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"#"
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[(set_attr "mode" "SI")])
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"!TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
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"@
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#
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#
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#
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movd\t{%1, %0|%0, %1}
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movd\t{%1, %0|%0, %1}"
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[(set_attr "mode" "SI,SI,SI,DI,TI")
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(set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
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(define_insn "*zero_extendsidi2_32_1"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
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(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,rm,rm")))
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(clobber (reg:CC 17))]
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"!TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
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"@
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#
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#
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#
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movd\t{%1, %0|%0, %1}
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movd\t{%1, %0|%0, %1}"
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[(set_attr "mode" "SI,SI,SI,DI,TI")
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(set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
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(define_insn "zero_extendsidi2_rex64"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
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(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
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"TARGET_64BIT"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!?Y")
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(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,m,m")))]
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"TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
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"@
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mov\t{%k1, %k0|%k0, %k1}
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#"
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[(set_attr "type" "imovx,imov")
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(set_attr "mode" "SI,DI")])
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#
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movd\t{%1, %0|%0, %1}
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movd\t{%1, %0|%0, %1}"
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[(set_attr "type" "imovx,imov,mmxmov,ssemov")
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(set_attr "mode" "SI,DI,DI,TI")])
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(define_insn "*zero_extendsidi2_rex64_1"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!*?")
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(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,rm,rm")))]
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"TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
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"@
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mov\t{%k1, %k0|%k0, %k1}
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#
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movd\t{%1, %0|%0, %1}
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movd\t{%1, %0|%0, %1}"
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[(set_attr "type" "imovx,imov,mmxmov,ssemov")
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(set_attr "mode" "SI,DI,SI,SI")])
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(define_split
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[(set (match_operand:DI 0 "memory_operand" "")
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@ -3315,7 +3349,8 @@
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[(set (match_operand:DI 0 "nonimmediate_operand" "")
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(zero_extend:DI (match_operand:SI 1 "general_operand" "")))
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(clobber (reg:CC 17))]
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"!TARGET_64BIT && reload_completed"
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"!TARGET_64BIT && reload_completed
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&& !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])"
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[(set (match_dup 3) (match_dup 1))
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(set (match_dup 4) (const_int 0))]
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"split_di (&operands[0], 1, &operands[3], &operands[4]);")
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@ -21228,7 +21263,7 @@
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(vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
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(vec_duplicate:V4HI
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(truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
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(match_operand:SI 3 "immediate_operand" "i")))]
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(match_operand:SI 3 "const_0_to_15_operand" "N")))]
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"TARGET_SSE || TARGET_3DNOW_A"
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"pinsrw\t{%3, %2, %0|%0, %2, %3}"
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[(set_attr "type" "mmxcvt")
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@ -21238,7 +21273,7 @@
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
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(parallel
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[(match_operand:SI 2 "immediate_operand" "i")]))))]
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[(match_operand:SI 2 "const_0_to_3_operand" "N")]))))]
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"TARGET_SSE || TARGET_3DNOW_A"
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"pextrw\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "mmxcvt")
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@ -22924,7 +22959,7 @@
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(vec_duplicate:V8HI
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(truncate:HI
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(match_operand:SI 2 "nonimmediate_operand" "rm")))
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(match_operand:SI 3 "immediate_operand" "i")))]
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(match_operand:SI 3 "const_0_to_255_operand" "N")))]
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"TARGET_SSE2"
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"pinsrw\t{%3, %2, %0|%0, %2, %3}"
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[(set_attr "type" "ssecvt")
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@ -22935,7 +22970,7 @@
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(zero_extend:SI
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(vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
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(parallel
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[(match_operand:SI 2 "immediate_operand" "i")]))))]
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[(match_operand:SI 2 "const_0_to_7_operand" "N")]))))]
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"TARGET_SSE2"
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"pextrw\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "ssecvt")
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@ -1419,6 +1419,15 @@ convert_modes (enum machine_mode mode, enum machine_mode oldmode, rtx x, int uns
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return gen_lowpart (mode, x);
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}
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/* Converting from integer constant into mode is always equivalent to an
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subreg operation. */
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if (VECTOR_MODE_P (mode) && GET_MODE (x) == VOIDmode)
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{
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if (GET_MODE_BITSIZE (mode) != GET_MODE_BITSIZE (oldmode))
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abort ();
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return simplify_gen_subreg (mode, x, oldmode, 0);
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}
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temp = gen_reg_rtx (mode);
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convert_move (temp, x, unsignedp);
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return temp;
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