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ACLE intrinsics: BFloat16 load intrinsics for AArch32
2020-03-06 Delia Burduv <delia.burduv@arm.com> * config/arm/arm_neon.h (vld2_bf16): New. (vld2q_bf16): New. (vld3_bf16): New. (vld3q_bf16): New. (vld4_bf16): New. (vld4q_bf16): New. (vld2_dup_bf16): New. (vld2q_dup_bf16): New. (vld3_dup_bf16): New. (vld3q_dup_bf16): New. (vld4_dup_bf16): New. (vld4q_dup_bf16): New. * config/arm/arm_neon_builtins.def (vld2): Changed to VAR13 and added v4bf, v8bf (vld2_dup): Changed to VAR8 and added v4bf, v8bf (vld3): Changed to VAR13 and added v4bf, v8bf (vld3_dup): Changed to VAR8 and added v4bf, v8bf (vld4): Changed to VAR13 and added v4bf, v8bf (vld4_dup): Changed to VAR8 and added v4bf, v8bf * config/arm/iterators.md (VDXBF2): New iterator. *config/arm/neon.md (neon_vld2): Use new iterators. (neon_vld2_dup<mode): Use new iterators. (neon_vld3<mode>): Likewise. (neon_vld3qa<mode>): Likewise. (neon_vld3qb<mode>): Likewise. (neon_vld3_dup<mode>): Likewise. (neon_vld4<mode>): Likewise. (neon_vld4qa<mode>): Likewise. (neon_vld4qb<mode>): Likewise. (neon_vld4_dup<mode>): Likewise. (neon_vld2_dupv8bf): New. (neon_vld3_dupv8bf): Likewise. (neon_vld4_dupv8bf): Likewise. * gcc.target/arm/simd/bf16_vldn_1.c: New test.
This commit is contained in:
Delia Burduv
Kyrylo Tkachov
parent
ff22937572
commit
eb637e7604
@ -1,3 +1,39 @@
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2020-03-06 Delia Burduv <delia.burduv@arm.com>
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* config/arm/arm_neon.h (vld2_bf16): New.
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(vld2q_bf16): New.
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(vld3_bf16): New.
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(vld3q_bf16): New.
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(vld4_bf16): New.
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(vld4q_bf16): New.
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(vld2_dup_bf16): New.
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(vld2q_dup_bf16): New.
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(vld3_dup_bf16): New.
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(vld3q_dup_bf16): New.
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(vld4_dup_bf16): New.
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(vld4q_dup_bf16): New.
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* config/arm/arm_neon_builtins.def
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(vld2): Changed to VAR13 and added v4bf, v8bf
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(vld2_dup): Changed to VAR8 and added v4bf, v8bf
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(vld3): Changed to VAR13 and added v4bf, v8bf
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(vld3_dup): Changed to VAR8 and added v4bf, v8bf
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(vld4): Changed to VAR13 and added v4bf, v8bf
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(vld4_dup): Changed to VAR8 and added v4bf, v8bf
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* config/arm/iterators.md (VDXBF2): New iterator.
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*config/arm/neon.md (neon_vld2): Use new iterators.
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(neon_vld2_dup<mode): Use new iterators.
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(neon_vld3<mode>): Likewise.
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(neon_vld3qa<mode>): Likewise.
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(neon_vld3qb<mode>): Likewise.
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(neon_vld3_dup<mode>): Likewise.
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(neon_vld4<mode>): Likewise.
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(neon_vld4qa<mode>): Likewise.
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(neon_vld4qb<mode>): Likewise.
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(neon_vld4_dup<mode>): Likewise.
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(neon_vld2_dupv8bf): New.
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(neon_vld3_dupv8bf): Likewise.
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(neon_vld4_dupv8bf): Likewise.
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2020-03-06 Delia Burduv <delia.burduv@arm.com>
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* config/arm/arm_neon.h (bfloat16x4x2_t): New typedef.
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@ -19557,6 +19557,114 @@ vst4q_bf16 (bfloat16_t * __ptr, bfloat16x8x4_t __val)
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return __builtin_neon_vst4v8bf (__ptr, __bu.__o);
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}
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__extension__ extern __inline bfloat16x4x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld2_bf16 (bfloat16_t const * __ptr)
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{
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union { bfloat16x4x2_t __i; __builtin_neon_ti __o; } __rv;
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__rv.__o = __builtin_neon_vld2v4bf ((const __builtin_neon_hi *) __ptr);
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return __rv.__i;
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}
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__extension__ extern __inline bfloat16x8x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld2q_bf16 (const bfloat16_t * __ptr)
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{
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union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __rv;
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__rv.__o = __builtin_neon_vld2v8bf ((const __builtin_neon_hi *) __ptr);
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return __rv.__i;
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}
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__extension__ extern __inline bfloat16x4x3_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld3_bf16 (const bfloat16_t * __ptr)
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{
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union { bfloat16x4x3_t __i; __builtin_neon_ei __o; } __rv;
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__rv.__o = __builtin_neon_vld3v4bf ((const __builtin_neon_hi *) __ptr);
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return __rv.__i;
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}
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__extension__ extern __inline bfloat16x8x3_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld3q_bf16 (const bfloat16_t * __ptr)
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{
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union { bfloat16x8x3_t __i; __builtin_neon_ci __o; } __rv;
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__rv.__o = __builtin_neon_vld3v8bf ((const __builtin_neon_hi *) __ptr);
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return __rv.__i;
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}
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__extension__ extern __inline bfloat16x4x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld4_bf16 (const bfloat16_t * __ptr)
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{
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union { bfloat16x4x4_t __i; __builtin_neon_oi __o; } __rv;
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__rv.__o = __builtin_neon_vld4v4bf ((const __builtin_neon_hi *) __ptr);
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return __rv.__i;
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}
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__extension__ extern __inline bfloat16x8x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld4q_bf16 (const bfloat16_t * __ptr)
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{
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union { bfloat16x8x4_t __i; __builtin_neon_xi __o; } __rv;
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__rv.__o = __builtin_neon_vld4v8bf ((const __builtin_neon_hi *) __ptr);
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return __rv.__i;
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}
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__extension__ extern __inline bfloat16x4x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld2_dup_bf16 (const bfloat16_t * __ptr)
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{
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union { bfloat16x4x2_t __i; __builtin_neon_ti __o; } __rv;
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__rv.__o = __builtin_neon_vld2_dupv4bf ((const __builtin_neon_hi *) __ptr);
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return __rv.__i;
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}
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__extension__ extern __inline bfloat16x8x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld2q_dup_bf16 (const bfloat16_t * __ptr)
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{
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union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __rv;
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__rv.__o = __builtin_neon_vld2_dupv8bf ((const __builtin_neon_hi *) __ptr);
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return __rv.__i;
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}
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__extension__ extern __inline bfloat16x4x3_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld3_dup_bf16 (const bfloat16_t * __ptr)
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{
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union { bfloat16x4x3_t __i; __builtin_neon_ei __o; } __rv;
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__rv.__o = __builtin_neon_vld3_dupv4bf ((const __builtin_neon_hi *) __ptr);
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return __rv.__i;
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}
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__extension__ extern __inline bfloat16x8x3_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld3q_dup_bf16 (const bfloat16_t * __ptr)
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{
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union { bfloat16x8x3_t __i; __builtin_neon_ci __o; } __rv;
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__rv.__o = __builtin_neon_vld3_dupv8bf ((const __builtin_neon_hi *) __ptr);
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return __rv.__i;
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}
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__extension__ extern __inline bfloat16x4x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld4_dup_bf16 (const bfloat16_t * __ptr)
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{
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union { bfloat16x4x4_t __i; __builtin_neon_oi __o; } __rv;
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__rv.__o = __builtin_neon_vld4_dupv4bf ((const __builtin_neon_hi *) __ptr);
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return __rv.__i;
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}
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__extension__ extern __inline bfloat16x8x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vld4q_dup_bf16 (const bfloat16_t * __ptr)
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{
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union { bfloat16x8x4_t __i; __builtin_neon_xi __o; } __rv;
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__rv.__o = __builtin_neon_vld4_dupv8bf ((const __builtin_neon_hi *) __ptr);
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return __rv.__i;
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}
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#pragma GCC pop_options
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#ifdef __cplusplus
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@ -320,29 +320,29 @@ VAR12 (STORE1, vst1,
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v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di)
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VAR12 (STORE1LANE, vst1_lane,
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v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di)
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VAR11 (LOAD1, vld2,
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v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf)
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VAR13 (LOAD1, vld2,
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v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v4bf, v8bf)
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VAR9 (LOAD1LANE, vld2_lane,
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v8qi, v4hi, v4hf, v2si, v2sf, v8hi, v8hf, v4si, v4sf)
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VAR6 (LOAD1, vld2_dup, v8qi, v4hi, v4hf, v2si, v2sf, di)
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VAR8 (LOAD1, vld2_dup, v8qi, v4hi, v4hf, v2si, v2sf, di, v4bf, v8bf)
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VAR13 (STORE1, vst2,
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v8qi, v4hi, v4hf, v4bf, v2si, v2sf, di, v16qi, v8hi, v8hf, v8bf, v4si, v4sf)
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VAR9 (STORE1LANE, vst2_lane,
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v8qi, v4hi, v4hf, v2si, v2sf, v8hi, v8hf, v4si, v4sf)
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VAR11 (LOAD1, vld3,
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v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf)
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VAR13 (LOAD1, vld3,
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v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v4bf, v8bf)
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VAR9 (LOAD1LANE, vld3_lane,
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v8qi, v4hi, v4hf, v2si, v2sf, v8hi, v8hf, v4si, v4sf)
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VAR6 (LOAD1, vld3_dup, v8qi, v4hi, v4hf, v2si, v2sf, di)
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VAR8 (LOAD1, vld3_dup, v8qi, v4hi, v4hf, v2si, v2sf, di, v4bf, v8bf)
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VAR13 (STORE1, vst3,
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v8qi, v4hi, v4hf, v4bf, v2si, v2sf, di, v16qi, v8hi, v8hf, v8bf, v4si, v4sf)
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VAR9 (STORE1LANE, vst3_lane,
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v8qi, v4hi, v4hf, v2si, v2sf, v8hi, v8hf, v4si, v4sf)
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VAR11 (LOAD1, vld4,
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v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf)
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VAR13 (LOAD1, vld4,
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v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v4bf, v8bf)
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VAR9 (LOAD1LANE, vld4_lane,
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v8qi, v4hi, v4hf, v2si, v2sf, v8hi, v8hf, v4si, v4sf)
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VAR6 (LOAD1, vld4_dup, v8qi, v4hi, v4hf, v2si, v2sf, di)
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VAR8 (LOAD1, vld4_dup, v8qi, v4hi, v4hf, v2si, v2sf, di, v4bf, v8bf)
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VAR13 (STORE1, vst4,
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v8qi, v4hi, v4hf, v4bf, v2si, v2sf, di, v16qi, v8hi, v8hf, v8bf, v4si, v4sf)
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VAR9 (STORE1LANE, vst4_lane,
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@ -87,6 +87,9 @@
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;; Double-width vector modes plus 64-bit elements, including V4BF.
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(define_mode_iterator VDXBF [V8QI V4HI V4HF (V4BF "TARGET_BF16_SIMD") V2SI V2SF DI])
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;; Double-width vector modes plus 64-bit elements, V4BF and V8BF.
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(define_mode_iterator VDXBF2 [V8QI V4HI V4HF V2SI V2SF DI (V4BF "TARGET_BF16_SIMD") (V8BF ("TARGET_BF16_SIMD"))])
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;; Double-width vector modes plus 64-bit elements,
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;; with V4BFmode added, suitable for moves.
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(define_mode_iterator VDXMOV [V8QI V4HI V4HF V4BF V2SI V2SF DI])
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@ -5428,7 +5428,7 @@ if (BYTES_BIG_ENDIAN)
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(define_insn "neon_vld2<mode>"
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[(set (match_operand:TI 0 "s_register_operand" "=w")
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(unspec:TI [(match_operand:TI 1 "neon_struct_operand" "Um")
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(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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(unspec:VDXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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UNSPEC_VLD2))]
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"TARGET_NEON"
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{
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@ -5453,7 +5453,7 @@ if (BYTES_BIG_ENDIAN)
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(define_insn "neon_vld2<mode>"
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[(set (match_operand:OI 0 "s_register_operand" "=w")
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(unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
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(unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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(unspec:VQ2BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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UNSPEC_VLD2))]
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"TARGET_NEON"
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"vld2.<V_sz_elem>\t%h0, %A1"
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@ -5516,7 +5516,7 @@ if (BYTES_BIG_ENDIAN)
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(define_insn "neon_vld2_dup<mode>"
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[(set (match_operand:TI 0 "s_register_operand" "=w")
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(unspec:TI [(match_operand:<V_two_elem> 1 "neon_struct_operand" "Um")
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(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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(unspec:VDXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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UNSPEC_VLD2_DUP))]
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"TARGET_NEON"
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{
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@ -5531,6 +5531,27 @@ if (BYTES_BIG_ENDIAN)
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(const_string "neon_load1_1reg<q>")))]
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)
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(define_insn "neon_vld2_dupv8bf"
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[(set (match_operand:OI 0 "s_register_operand" "=w")
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(unspec:OI [(match_operand:V2BF 1 "neon_struct_operand" "Um")
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(unspec:V8BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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UNSPEC_VLD2_DUP))]
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"TARGET_BF16_SIMD"
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{
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rtx ops[5];
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int tabbase = REGNO (operands[0]);
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ops[4] = operands[1];
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ops[0] = gen_rtx_REG (V4BFmode, tabbase);
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ops[1] = gen_rtx_REG (V4BFmode, tabbase + 2);
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ops[2] = gen_rtx_REG (V4BFmode, tabbase + 4);
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ops[3] = gen_rtx_REG (V4BFmode, tabbase + 6);
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output_asm_insn ("vld2.16\t{%P0, %P1, %P2, %P3}, %A4", ops);
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return "";
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}
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[(set_attr "type" "neon_load2_all_lanes_q")]
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)
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(define_expand "vec_store_lanesti<mode>"
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[(set (match_operand:TI 0 "neon_struct_operand")
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(unspec:TI [(match_operand:TI 1 "s_register_operand")
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@ -5637,7 +5658,7 @@ if (BYTES_BIG_ENDIAN)
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(define_insn "neon_vld3<mode>"
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[(set (match_operand:EI 0 "s_register_operand" "=w")
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(unspec:EI [(match_operand:EI 1 "neon_struct_operand" "Um")
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(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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(unspec:VDXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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UNSPEC_VLD3))]
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"TARGET_NEON"
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{
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@ -5665,7 +5686,7 @@ if (BYTES_BIG_ENDIAN)
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(define_expand "neon_vld3<mode>"
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[(match_operand:CI 0 "s_register_operand")
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(match_operand:CI 1 "neon_struct_operand")
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(unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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(unspec:VQ2BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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"TARGET_NEON"
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{
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rtx mem;
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@ -5680,7 +5701,7 @@ if (BYTES_BIG_ENDIAN)
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(define_insn "neon_vld3qa<mode>"
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[(set (match_operand:CI 0 "s_register_operand" "=w")
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(unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
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(unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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(unspec:VQ2BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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UNSPEC_VLD3A))]
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"TARGET_NEON"
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{
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@ -5700,7 +5721,7 @@ if (BYTES_BIG_ENDIAN)
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[(set (match_operand:CI 0 "s_register_operand" "=w")
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(unspec:CI [(match_operand:EI 1 "neon_struct_operand" "Um")
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(match_operand:CI 2 "s_register_operand" "0")
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(unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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(unspec:VQ2BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
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UNSPEC_VLD3B))]
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"TARGET_NEON"
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{
|
||||
@ -5777,7 +5798,7 @@ if (BYTES_BIG_ENDIAN)
|
||||
(define_insn "neon_vld3_dup<mode>"
|
||||
[(set (match_operand:EI 0 "s_register_operand" "=w")
|
||||
(unspec:EI [(match_operand:<V_three_elem> 1 "neon_struct_operand" "Um")
|
||||
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
(unspec:VDXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
UNSPEC_VLD3_DUP))]
|
||||
"TARGET_NEON"
|
||||
{
|
||||
@ -5800,6 +5821,26 @@ if (BYTES_BIG_ENDIAN)
|
||||
(const_string "neon_load3_all_lanes<q>")
|
||||
(const_string "neon_load1_1reg<q>")))])
|
||||
|
||||
(define_insn "neon_vld3_dupv8bf"
|
||||
[(set (match_operand:CI 0 "s_register_operand" "=w")
|
||||
(unspec:CI [(match_operand:V2BF 1 "neon_struct_operand" "Um")
|
||||
(unspec:V8BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
UNSPEC_VLD2_DUP))]
|
||||
"TARGET_BF16_SIMD"
|
||||
{
|
||||
rtx ops[4];
|
||||
int tabbase = REGNO (operands[0]);
|
||||
|
||||
ops[3] = operands[1];
|
||||
ops[0] = gen_rtx_REG (V4BFmode, tabbase);
|
||||
ops[1] = gen_rtx_REG (V4BFmode, tabbase + 2);
|
||||
ops[2] = gen_rtx_REG (V4BFmode, tabbase + 4);
|
||||
output_asm_insn ("vld3.16\t{%P0[], %P1[], %P2[]}, %A3", ops);
|
||||
return "";
|
||||
}
|
||||
[(set_attr "type" "neon_load3_all_lanes_q")]
|
||||
)
|
||||
|
||||
(define_expand "vec_store_lanesei<mode>"
|
||||
[(set (match_operand:EI 0 "neon_struct_operand")
|
||||
(unspec:EI [(match_operand:EI 1 "s_register_operand")
|
||||
@ -5955,7 +5996,7 @@ if (BYTES_BIG_ENDIAN)
|
||||
(define_insn "neon_vld4<mode>"
|
||||
[(set (match_operand:OI 0 "s_register_operand" "=w")
|
||||
(unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um")
|
||||
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
(unspec:VDXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
UNSPEC_VLD4))]
|
||||
"TARGET_NEON"
|
||||
{
|
||||
@ -5983,7 +6024,7 @@ if (BYTES_BIG_ENDIAN)
|
||||
(define_expand "neon_vld4<mode>"
|
||||
[(match_operand:XI 0 "s_register_operand")
|
||||
(match_operand:XI 1 "neon_struct_operand")
|
||||
(unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
(unspec:VQ2BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
"TARGET_NEON"
|
||||
{
|
||||
rtx mem;
|
||||
@ -5998,7 +6039,7 @@ if (BYTES_BIG_ENDIAN)
|
||||
(define_insn "neon_vld4qa<mode>"
|
||||
[(set (match_operand:XI 0 "s_register_operand" "=w")
|
||||
(unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
|
||||
(unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
(unspec:VQ2BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
UNSPEC_VLD4A))]
|
||||
"TARGET_NEON"
|
||||
{
|
||||
@ -6019,7 +6060,7 @@ if (BYTES_BIG_ENDIAN)
|
||||
[(set (match_operand:XI 0 "s_register_operand" "=w")
|
||||
(unspec:XI [(match_operand:OI 1 "neon_struct_operand" "Um")
|
||||
(match_operand:XI 2 "s_register_operand" "0")
|
||||
(unspec:VQ2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
(unspec:VQ2BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
UNSPEC_VLD4B))]
|
||||
"TARGET_NEON"
|
||||
{
|
||||
@ -6099,7 +6140,7 @@ if (BYTES_BIG_ENDIAN)
|
||||
(define_insn "neon_vld4_dup<mode>"
|
||||
[(set (match_operand:OI 0 "s_register_operand" "=w")
|
||||
(unspec:OI [(match_operand:<V_four_elem> 1 "neon_struct_operand" "Um")
|
||||
(unspec:VDX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
(unspec:VDXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
UNSPEC_VLD4_DUP))]
|
||||
"TARGET_NEON"
|
||||
{
|
||||
@ -6125,6 +6166,27 @@ if (BYTES_BIG_ENDIAN)
|
||||
(const_string "neon_load1_1reg<q>")))]
|
||||
)
|
||||
|
||||
(define_insn "neon_vld4_dupv8bf"
|
||||
[(set (match_operand:XI 0 "s_register_operand" "=w")
|
||||
(unspec:XI [(match_operand:V2BF 1 "neon_struct_operand" "Um")
|
||||
(unspec:V8BF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
UNSPEC_VLD2_DUP))]
|
||||
"TARGET_BF16_SIMD"
|
||||
{
|
||||
rtx ops[5];
|
||||
int tabbase = REGNO (operands[0]);
|
||||
|
||||
ops[4] = operands[1];
|
||||
ops[0] = gen_rtx_REG (V4BFmode, tabbase);
|
||||
ops[1] = gen_rtx_REG (V4BFmode, tabbase + 2);
|
||||
ops[2] = gen_rtx_REG (V4BFmode, tabbase + 4);
|
||||
ops[3] = gen_rtx_REG (V4BFmode, tabbase + 6);
|
||||
output_asm_insn ("vld4.16\t{%P0[], %P1[], %P2[], %P3[]}, %A4", ops);
|
||||
return "";
|
||||
}
|
||||
[(set_attr "type" "neon_load4_all_lanes_q")]
|
||||
)
|
||||
|
||||
(define_expand "vec_store_lanesoi<mode>"
|
||||
[(set (match_operand:OI 0 "neon_struct_operand")
|
||||
(unspec:OI [(match_operand:OI 1 "s_register_operand")
|
||||
|
||||
@ -1,3 +1,7 @@
|
||||
2020-03-06 Delia Burduv <delia.burduv@arm.com>
|
||||
|
||||
* gcc.target/arm/simd/bf16_vldn_1.c: New test.
|
||||
|
||||
2020-03-06 Delia Burduv <delia.burduv@arm.com>
|
||||
|
||||
* gcc.target/arm/simd/bf16_vstn_1.c: New test.
|
||||
|
||||
152
gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c
Normal file
152
gcc/testsuite/gcc.target/arm/simd/bf16_vldn_1.c
Normal file
@ -0,0 +1,152 @@
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
|
||||
/* { dg-add-options arm_v8_2a_bf16_neon } */
|
||||
/* { dg-additional-options "-save-temps -O2 -mfloat-abi=hard" } */
|
||||
/* { dg-final { check-function-bodies "**" "" } } */
|
||||
|
||||
#include "arm_neon.h"
|
||||
|
||||
|
||||
/*
|
||||
**test_vld2_bf16:
|
||||
** ...
|
||||
** vld2.16 {d0-d1}, \[r0\]
|
||||
** bx lr
|
||||
*/
|
||||
bfloat16x4x2_t
|
||||
test_vld2_bf16 (bfloat16_t * ptr)
|
||||
{
|
||||
return vld2_bf16 (ptr);
|
||||
}
|
||||
|
||||
/*
|
||||
**test_vld2q_bf16:
|
||||
** ...
|
||||
** vld2.16 {d0-d3}, \[r0\]
|
||||
** bx lr
|
||||
*/
|
||||
bfloat16x8x2_t
|
||||
test_vld2q_bf16 (bfloat16_t * ptr)
|
||||
{
|
||||
return vld2q_bf16 (ptr);
|
||||
}
|
||||
|
||||
/*
|
||||
**test_vld2_dup_bf16:
|
||||
** ...
|
||||
** vld2.16 {d0\[\], d1\[\]}, \[r0\]
|
||||
** bx lr
|
||||
*/
|
||||
bfloat16x4x2_t
|
||||
test_vld2_dup_bf16 (bfloat16_t * ptr)
|
||||
{
|
||||
return vld2_dup_bf16 (ptr);
|
||||
}
|
||||
|
||||
/*
|
||||
**test_vld2q_dup_bf16:
|
||||
** ...
|
||||
** vld2.16 {d0, d1, d2, d3}, \[r0\]
|
||||
** bx lr
|
||||
*/
|
||||
bfloat16x8x2_t
|
||||
test_vld2q_dup_bf16 (bfloat16_t * ptr)
|
||||
{
|
||||
return vld2q_dup_bf16 (ptr);
|
||||
}
|
||||
|
||||
/*
|
||||
**test_vld3_bf16:
|
||||
** ...
|
||||
** vld3.16 {d0-d2}, \[r0\]
|
||||
** bx lr
|
||||
*/
|
||||
bfloat16x4x3_t
|
||||
test_vld3_bf16 (bfloat16_t * ptr)
|
||||
{
|
||||
return vld3_bf16 (ptr);
|
||||
}
|
||||
|
||||
/*
|
||||
**test_vld3q_bf16:
|
||||
** ...
|
||||
** vld3.16 {d1, d3, d5}, \[r0\]
|
||||
** bx lr
|
||||
*/
|
||||
bfloat16x8x3_t
|
||||
test_vld3q_bf16 (bfloat16_t * ptr)
|
||||
{
|
||||
return vld3q_bf16 (ptr);
|
||||
}
|
||||
|
||||
/*
|
||||
**test_vld3_dup_bf16:
|
||||
** ...
|
||||
** vld3.16 {d0\[\], d1\[\], d2\[\]}, \[r0\]
|
||||
** bx lr
|
||||
*/
|
||||
bfloat16x4x3_t
|
||||
test_vld3_dup_bf16 (bfloat16_t * ptr)
|
||||
{
|
||||
return vld3_dup_bf16 (ptr);
|
||||
}
|
||||
|
||||
/*
|
||||
**test_vld3q_dup_bf16:
|
||||
** ...
|
||||
** vld3.16 {d0\[\], d1\[\], d2\[\]}, \[r0\]
|
||||
** bx lr
|
||||
*/
|
||||
bfloat16x8x3_t
|
||||
test_vld3q_dup_bf16 (bfloat16_t * ptr)
|
||||
{
|
||||
return vld3q_dup_bf16 (ptr);
|
||||
}
|
||||
|
||||
/*
|
||||
**test_vld4_bf16:
|
||||
** ...
|
||||
** vld4.16 {d0-d3}, \[r0\]
|
||||
** bx lr
|
||||
*/
|
||||
bfloat16x4x4_t
|
||||
test_vld4_bf16 (bfloat16_t * ptr)
|
||||
{
|
||||
return vld4_bf16 (ptr);
|
||||
}
|
||||
|
||||
/*
|
||||
**test_vld4q_bf16:
|
||||
** ...
|
||||
** vld4.16 {d1, d3, d5, d7}, \[r0\]
|
||||
** bx lr
|
||||
*/
|
||||
bfloat16x8x4_t
|
||||
test_vld4q_bf16 (bfloat16_t * ptr)
|
||||
{
|
||||
return vld4q_bf16 (ptr);
|
||||
}
|
||||
|
||||
/*
|
||||
**test_vld4_dup_bf16:
|
||||
** ...
|
||||
** vld4.16 {d0\[\], d1\[\], d2\[\], d3\[\]}, \[r0\]
|
||||
** bx lr
|
||||
*/
|
||||
bfloat16x4x4_t
|
||||
test_vld4_dup_bf16 (bfloat16_t * ptr)
|
||||
{
|
||||
return vld4_dup_bf16 (ptr);
|
||||
}
|
||||
|
||||
/*
|
||||
**test_vld4q_dup_bf16:
|
||||
** ...
|
||||
** vld4.16 {d0\[\], d1\[\], d2\[\], d3\[\]}, \[r0\]
|
||||
** bx lr
|
||||
*/
|
||||
bfloat16x8x4_t
|
||||
test_vld4q_dup_bf16 (bfloat16_t * ptr)
|
||||
{
|
||||
return vld4q_dup_bf16 (ptr);
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user