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i386.md (FPSR_REG): Remove.
* config/i386/i386.md (FPSR_REG): Remove. (x86_fnstcw_1): Use (const_int 0) instead of FPCR_REG. (x86_fldcw_1): Remove insn pattern. (fnstenv): Do not clobber FPCR_REG. (fldenv): Ditto. * config/i386/i386.h (FIXED_REGISTERS) Remove fpsr register. (CALL_USED_REGISTERS): Ditto. (REG_ALLOC_ORDER): Ditto. (REG_CLASS_CONTENTS): Ditto. (HI_REGISTER_NAMES): Ditto. (ADDITIONAL_REGISTER_NAMES): Use defines instead of numerical constants. * config/i386/i386.c (regclass_map): Remove fpsr register. (dbx_register_map): Ditto. (dbx64_register_map): Ditto. (svr4_dbx_register_map): Ditto. (print_reg): Do not handle FPCR_REG. testsuite/ChangeLog: * gcc.dg/rtl/x86_64/dfinit.c: Update scan-rtl-dump string. * gcc.dg/rtl/x86_64/times-two.c.before-df.c: Ditto. * gcc.target/i386/pr79804.c (foo): Use register "19", not "20". From-SVN: r264676
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
24676f1215
commit
eaa17c21ba
@ -1,3 +1,23 @@
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2018-09-27 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (FPSR_REG): Remove.
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(x86_fnstcw_1): Use (const_int 0) instead of FPCR_REG.
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(x86_fldcw_1): Remove insn pattern.
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(fnstenv): Do not clobber FPCR_REG.
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(fldenv): Ditto.
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* config/i386/i386.h (FIXED_REGISTERS) Remove fpsr register.
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(CALL_USED_REGISTERS): Ditto.
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(REG_ALLOC_ORDER): Ditto.
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(REG_CLASS_CONTENTS): Ditto.
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(HI_REGISTER_NAMES): Ditto.
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(ADDITIONAL_REGISTER_NAMES): Use defines instead
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of numerical constants.
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* config/i386/i386.c (regclass_map): Remove fpsr register.
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(dbx_register_map): Ditto.
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(dbx64_register_map): Ditto.
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(svr4_dbx_register_map): Ditto.
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(print_reg): Do not handle FPCR_REG.
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2018-09-27 Segher Boessenkool <segher@kernel.crashing.org>
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PR target/87149
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@ -241,10 +241,8 @@ enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
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/* FP registers */
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FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
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FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
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/* arg pointer */
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NON_Q_REGS,
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/* flags, fpsr, fpcr, frame */
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NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
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/* arg pointer, flags, fpsr, frame */
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NON_Q_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
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/* SSE registers */
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SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS,
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SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
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@ -273,7 +271,7 @@ int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
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{
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0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
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12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
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-1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
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-1, -1, -1, -1, /* arg, flags, fpsr, frame */
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21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
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29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
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-1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
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@ -289,7 +287,7 @@ int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
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{
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0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
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33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
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-1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
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-1, -1, -1, -1, /* arg, flags, fpsr, frame */
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17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
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41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
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8,9,10,11,12,13,14,15, /* extended integer registers */
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@ -357,7 +355,7 @@ int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
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{
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0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
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11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
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-1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
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-1, 9, -1, -1, /* arg, flags, fpsr, frame */
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21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
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29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
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-1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
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@ -17372,8 +17370,7 @@ print_reg (rtx x, int code, FILE *file)
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if (regno == ARG_POINTER_REGNUM
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|| regno == FRAME_POINTER_REGNUM
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|| regno == FPSR_REG
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|| regno == FPCR_REG)
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|| regno == FPSR_REG)
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{
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output_operand_lossage
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("invalid use of register '%s'", reg_names[regno]);
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@ -1026,8 +1026,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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#define FIXED_REGISTERS \
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/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
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{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
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/*arg,flags,fpsr,fpcr,frame*/ \
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1, 1, 1, 1, 1, \
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/*arg,flags,fpsr,frame*/ \
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1, 1, 1, 1, \
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/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
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0, 0, 0, 0, 0, 0, 0, 0, \
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/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
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@ -1063,8 +1063,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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#define CALL_USED_REGISTERS \
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/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
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{ 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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/*arg,flags,fpsr,fpcr,frame*/ \
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1, 1, 1, 1, 1, \
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/*arg,flags,fpsr,frame*/ \
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1, 1, 1, 1, \
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/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
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1, 1, 1, 1, 1, 1, 6, 6, \
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/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \
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@ -1089,12 +1089,12 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
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so this is just empty initializer for array. */
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#define REG_ALLOC_ORDER \
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{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
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18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
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33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
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48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \
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63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76 }
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#define REG_ALLOC_ORDER \
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{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
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16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
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32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
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48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
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64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 }
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/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
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to be rearranged based on a particular function. When using sse math,
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@ -1315,7 +1315,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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For any two classes, it is very desirable that there be another
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class that represents their union.
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The flags, fpsr and fpcr registers are in no class. */
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The flags and fpsr registers are in no class. */
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enum reg_class
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{
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@ -1411,36 +1411,36 @@ enum reg_class
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TARGET_CONDITIONAL_REGISTER_USAGE. */
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#define REG_CLASS_CONTENTS \
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{ { 0x0, 0x0, 0x0 }, /* NO_REGS */ \
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{ 0x01, 0x0, 0x0 }, /* AREG */ \
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{ 0x02, 0x0, 0x0 }, /* DREG */ \
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{ 0x04, 0x0, 0x0 }, /* CREG */ \
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{ 0x08, 0x0, 0x0 }, /* BREG */ \
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{ 0x10, 0x0, 0x0 }, /* SIREG */ \
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{ 0x20, 0x0, 0x0 }, /* DIREG */ \
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{ 0x03, 0x0, 0x0 }, /* AD_REGS */ \
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{ 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
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{ 0x0f, 0x0, 0x0 }, /* Q_REGS */ \
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{ 0x1100f0, 0x0, 0x0 }, /* NON_Q_REGS */ \
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{ 0x7e, 0x1fe0, 0x0 }, /* TLS_GOTBASE_REGS */ \
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{ 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \
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{ 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
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{ 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \
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{ 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
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{ 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
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{ 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
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{ 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
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{ 0x1fe00000, 0x0, 0x0 }, /* NO_REX_SSE_REGS */ \
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{ 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \
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{ 0x1fe00000, 0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \
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{ 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \
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{ 0x1fe0ff00, 0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \
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{ 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \
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{ 0x1ff100ff, 0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \
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{ 0x1ff1ffff, 0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \
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{ 0x0, 0x0, 0x1fc0 }, /* MASK_REGS */ \
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{ 0x0, 0x0, 0x1fe0 }, /* ALL_MASK_REGS */ \
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{ 0xffffffff, 0xffffffff, 0x1fff } /* ALL_REGS */ \
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{ { 0x0, 0x0, 0x0 }, /* NO_REGS */ \
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{ 0x01, 0x0, 0x0 }, /* AREG */ \
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{ 0x02, 0x0, 0x0 }, /* DREG */ \
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{ 0x04, 0x0, 0x0 }, /* CREG */ \
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{ 0x08, 0x0, 0x0 }, /* BREG */ \
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{ 0x10, 0x0, 0x0 }, /* SIREG */ \
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{ 0x20, 0x0, 0x0 }, /* DIREG */ \
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{ 0x03, 0x0, 0x0 }, /* AD_REGS */ \
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{ 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
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{ 0x0f, 0x0, 0x0 }, /* Q_REGS */ \
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{ 0x900f0, 0x0, 0x0 }, /* NON_Q_REGS */ \
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{ 0x7e, 0xff0, 0x0 }, /* TLS_GOTBASE_REGS */ \
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{ 0x7f, 0xff0, 0x0 }, /* INDEX_REGS */ \
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{ 0x900ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
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{ 0x900ff, 0xff0, 0x0 }, /* GENERAL_REGS */ \
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{ 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
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{ 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
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{ 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
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{ 0x100000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
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{ 0xff00000, 0x0, 0x0 }, /* NO_REX_SSE_REGS */ \
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{ 0xff00000, 0xff000, 0x0 }, /* SSE_REGS */ \
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{ 0xff00000, 0xfffff000, 0xf }, /* ALL_SSE_REGS */ \
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{ 0xf0000000, 0xf, 0x0 }, /* MMX_REGS */ \
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{ 0xff0ff00, 0xfffff000, 0xf }, /* FLOAT_SSE_REGS */ \
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{ 0x9ffff, 0xff0, 0x0 }, /* FLOAT_INT_REGS */ \
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{ 0xff900ff, 0xfffffff0, 0xf }, /* INT_SSE_REGS */ \
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{ 0xff9ffff, 0xfffffff0, 0xf }, /* FLOAT_INT_SSE_REGS */ \
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{ 0x0, 0x0, 0xfe0 }, /* MASK_REGS */ \
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{ 0x0, 0x0, 0xff0 }, /* ALL_MASK_REGS */ \
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{ 0xffffffff, 0xffffffff, 0xfff } /* ALL_REGS */ \
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}
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/* The same information, inverted:
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@ -2022,7 +2022,7 @@ do { \
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#define HI_REGISTER_NAMES \
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{"ax","dx","cx","bx","si","di","bp","sp", \
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"st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \
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"argp", "flags", "fpsr", "fpcr", "frame", \
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"argp", "flags", "fpsr", "frame", \
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"xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
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"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
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@ -2037,29 +2037,31 @@ do { \
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/* Table of additional register names to use in user input. */
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#define ADDITIONAL_REGISTER_NAMES \
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{ { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
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{ "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
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{ "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
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{ "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
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{ "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
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{ "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
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{ "ymm0", 21}, { "ymm1", 22}, { "ymm2", 23}, { "ymm3", 24}, \
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{ "ymm4", 25}, { "ymm5", 26}, { "ymm6", 27}, { "ymm7", 28}, \
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{ "ymm8", 45}, { "ymm9", 46}, { "ymm10", 47}, { "ymm11", 48}, \
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{ "ymm12", 49}, { "ymm13", 50}, { "ymm14", 51}, { "ymm15", 52}, \
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{ "ymm16", 53}, { "ymm17", 54}, { "ymm18", 55}, { "ymm19", 56}, \
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{ "ymm20", 57}, { "ymm21", 58}, { "ymm22", 59}, { "ymm23", 60}, \
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{ "ymm24", 61}, { "ymm25", 62}, { "ymm26", 63}, { "ymm27", 64}, \
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{ "ymm28", 65}, { "ymm29", 66}, { "ymm30", 67}, { "ymm31", 68}, \
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{ "zmm0", 21}, { "zmm1", 22}, { "zmm2", 23}, { "zmm3", 24}, \
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{ "zmm4", 25}, { "zmm5", 26}, { "zmm6", 27}, { "zmm7", 28}, \
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{ "zmm8", 45}, { "zmm9", 46}, { "zmm10", 47}, { "zmm11", 48}, \
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{ "zmm12", 49}, { "zmm13", 50}, { "zmm14", 51}, { "zmm15", 52}, \
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{ "zmm16", 53}, { "zmm17", 54}, { "zmm18", 55}, { "zmm19", 56}, \
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{ "zmm20", 57}, { "zmm21", 58}, { "zmm22", 59}, { "zmm23", 60}, \
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{ "zmm24", 61}, { "zmm25", 62}, { "zmm26", 63}, { "zmm27", 64}, \
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{ "zmm28", 65}, { "zmm29", 66}, { "zmm30", 67}, { "zmm31", 68} }
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#define ADDITIONAL_REGISTER_NAMES \
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{ \
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{ "eax", AX_REG }, { "edx", DX_REG }, { "ecx", CX_REG }, { "ebx", BX_REG }, \
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{ "esi", SI_REG }, { "edi", DI_REG }, { "ebp", BP_REG }, { "esp", SP_REG }, \
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{ "rax", AX_REG }, { "rdx", DX_REG }, { "rcx", CX_REG }, { "rbx", BX_REG }, \
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{ "rsi", SI_REG }, { "rdi", DI_REG }, { "rbp", BP_REG }, { "rsp", SP_REG }, \
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{ "al", AX_REG }, { "dl", DX_REG }, { "cl", CX_REG }, { "bl", BX_REG }, \
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{ "ah", AX_REG }, { "dh", DX_REG }, { "ch", CX_REG }, { "bh", BX_REG }, \
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{ "ymm0", XMM0_REG }, { "ymm1", XMM1_REG }, { "ymm2", XMM2_REG }, { "ymm3", XMM3_REG }, \
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{ "ymm4", XMM4_REG }, { "ymm5", XMM5_REG }, { "ymm6", XMM6_REG }, { "ymm7", XMM7_REG }, \
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{ "ymm8", XMM8_REG }, { "ymm9", XMM9_REG }, { "ymm10", XMM10_REG }, { "ymm11", XMM11_REG }, \
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{ "ymm12", XMM12_REG }, { "ymm13", XMM13_REG }, { "ymm14", XMM14_REG }, { "ymm15", XMM15_REG }, \
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{ "ymm16", XMM16_REG }, { "ymm17", XMM17_REG }, { "ymm18", XMM18_REG }, { "ymm19", XMM19_REG }, \
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{ "ymm20", XMM20_REG }, { "ymm21", XMM21_REG }, { "ymm22", XMM22_REG }, { "ymm23", XMM23_REG }, \
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{ "ymm24", XMM24_REG }, { "ymm25", XMM25_REG }, { "ymm26", XMM26_REG }, { "ymm27", XMM27_REG }, \
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{ "ymm28", XMM28_REG }, { "ymm29", XMM29_REG }, { "ymm30", XMM30_REG }, { "ymm31", XMM31_REG }, \
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{ "zmm0", XMM0_REG }, { "zmm1", XMM1_REG }, { "zmm2", XMM2_REG }, { "zmm3", XMM3_REG }, \
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{ "zmm4", XMM4_REG }, { "zmm5", XMM5_REG }, { "zmm6", XMM6_REG }, { "zmm7", XMM7_REG }, \
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{ "zmm8", XMM8_REG }, { "zmm9", XMM9_REG }, { "zmm10", XMM10_REG }, { "zmm11", XMM11_REG }, \
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{ "zmm12", XMM12_REG }, { "zmm13", XMM13_REG }, { "zmm14", XMM14_REG }, { "zmm15", XMM15_REG }, \
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{ "zmm16", XMM16_REG }, { "zmm17", XMM17_REG }, { "zmm18", XMM18_REG }, { "zmm19", XMM19_REG }, \
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{ "zmm20", XMM20_REG }, { "zmm21", XMM21_REG }, { "zmm22", XMM22_REG }, { "zmm23", XMM23_REG }, \
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{ "zmm24", XMM24_REG }, { "zmm25", XMM25_REG }, { "zmm26", XMM26_REG }, { "zmm27", XMM27_REG }, \
|
||||
{ "zmm28", XMM28_REG }, { "zmm29", XMM29_REG }, { "zmm30", XMM30_REG }, { "zmm31", XMM31_REG } \
|
||||
}
|
||||
|
||||
/* Note we are omitting these since currently I don't know how
|
||||
to get gcc to use these, since they want the same but different
|
||||
|
||||
@ -359,65 +359,64 @@
|
||||
(ARGP_REG 16)
|
||||
(FLAGS_REG 17)
|
||||
(FPSR_REG 18)
|
||||
(FPCR_REG 19)
|
||||
(FRAME_REG 20)
|
||||
(XMM0_REG 21)
|
||||
(XMM1_REG 22)
|
||||
(XMM2_REG 23)
|
||||
(XMM3_REG 24)
|
||||
(XMM4_REG 25)
|
||||
(XMM5_REG 26)
|
||||
(XMM6_REG 27)
|
||||
(XMM7_REG 28)
|
||||
(MM0_REG 29)
|
||||
(MM1_REG 30)
|
||||
(MM2_REG 31)
|
||||
(MM3_REG 32)
|
||||
(MM4_REG 33)
|
||||
(MM5_REG 34)
|
||||
(MM6_REG 35)
|
||||
(MM7_REG 36)
|
||||
(R8_REG 37)
|
||||
(R9_REG 38)
|
||||
(R10_REG 39)
|
||||
(R11_REG 40)
|
||||
(R12_REG 41)
|
||||
(R13_REG 42)
|
||||
(R14_REG 43)
|
||||
(R15_REG 44)
|
||||
(XMM8_REG 45)
|
||||
(XMM9_REG 46)
|
||||
(XMM10_REG 47)
|
||||
(XMM11_REG 48)
|
||||
(XMM12_REG 49)
|
||||
(XMM13_REG 50)
|
||||
(XMM14_REG 51)
|
||||
(XMM15_REG 52)
|
||||
(XMM16_REG 53)
|
||||
(XMM17_REG 54)
|
||||
(XMM18_REG 55)
|
||||
(XMM19_REG 56)
|
||||
(XMM20_REG 57)
|
||||
(XMM21_REG 58)
|
||||
(XMM22_REG 59)
|
||||
(XMM23_REG 60)
|
||||
(XMM24_REG 61)
|
||||
(XMM25_REG 62)
|
||||
(XMM26_REG 63)
|
||||
(XMM27_REG 64)
|
||||
(XMM28_REG 65)
|
||||
(XMM29_REG 66)
|
||||
(XMM30_REG 67)
|
||||
(XMM31_REG 68)
|
||||
(MASK0_REG 69)
|
||||
(MASK1_REG 70)
|
||||
(MASK2_REG 71)
|
||||
(MASK3_REG 72)
|
||||
(MASK4_REG 73)
|
||||
(MASK5_REG 74)
|
||||
(MASK6_REG 75)
|
||||
(MASK7_REG 76)
|
||||
(FIRST_PSEUDO_REG 77)
|
||||
(FRAME_REG 19)
|
||||
(XMM0_REG 20)
|
||||
(XMM1_REG 21)
|
||||
(XMM2_REG 22)
|
||||
(XMM3_REG 23)
|
||||
(XMM4_REG 24)
|
||||
(XMM5_REG 25)
|
||||
(XMM6_REG 26)
|
||||
(XMM7_REG 27)
|
||||
(MM0_REG 28)
|
||||
(MM1_REG 29)
|
||||
(MM2_REG 30)
|
||||
(MM3_REG 31)
|
||||
(MM4_REG 32)
|
||||
(MM5_REG 33)
|
||||
(MM6_REG 34)
|
||||
(MM7_REG 35)
|
||||
(R8_REG 36)
|
||||
(R9_REG 37)
|
||||
(R10_REG 38)
|
||||
(R11_REG 39)
|
||||
(R12_REG 40)
|
||||
(R13_REG 41)
|
||||
(R14_REG 42)
|
||||
(R15_REG 43)
|
||||
(XMM8_REG 44)
|
||||
(XMM9_REG 45)
|
||||
(XMM10_REG 46)
|
||||
(XMM11_REG 47)
|
||||
(XMM12_REG 48)
|
||||
(XMM13_REG 49)
|
||||
(XMM14_REG 50)
|
||||
(XMM15_REG 51)
|
||||
(XMM16_REG 52)
|
||||
(XMM17_REG 53)
|
||||
(XMM18_REG 54)
|
||||
(XMM19_REG 55)
|
||||
(XMM20_REG 56)
|
||||
(XMM21_REG 57)
|
||||
(XMM22_REG 58)
|
||||
(XMM23_REG 59)
|
||||
(XMM24_REG 60)
|
||||
(XMM25_REG 61)
|
||||
(XMM26_REG 62)
|
||||
(XMM27_REG 63)
|
||||
(XMM28_REG 64)
|
||||
(XMM29_REG 65)
|
||||
(XMM30_REG 66)
|
||||
(XMM31_REG 67)
|
||||
(MASK0_REG 68)
|
||||
(MASK1_REG 69)
|
||||
(MASK2_REG 70)
|
||||
(MASK3_REG 71)
|
||||
(MASK4_REG 72)
|
||||
(MASK5_REG 73)
|
||||
(MASK6_REG 74)
|
||||
(MASK7_REG 75)
|
||||
(FIRST_PSEUDO_REG 76)
|
||||
])
|
||||
|
||||
;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
|
||||
@ -5043,7 +5042,7 @@
|
||||
|
||||
(define_insn "x86_fnstcw_1"
|
||||
[(set (match_operand:HI 0 "memory_operand" "=m")
|
||||
(unspec:HI [(reg:HI FPCR_REG)] UNSPEC_FSTCW))]
|
||||
(unspec:HI [(const_int 0)] UNSPEC_FSTCW))]
|
||||
"TARGET_80387"
|
||||
"fnstcw\t%0"
|
||||
[(set (attr "length")
|
||||
@ -5051,19 +5050,6 @@
|
||||
(set_attr "mode" "HI")
|
||||
(set_attr "unit" "i387")
|
||||
(set_attr "bdver1_decode" "vector")])
|
||||
|
||||
(define_insn "x86_fldcw_1"
|
||||
[(set (reg:HI FPCR_REG)
|
||||
(unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
|
||||
"TARGET_80387"
|
||||
"fldcw\t%0"
|
||||
[(set (attr "length")
|
||||
(symbol_ref "ix86_attr_length_address_default (insn) + 2"))
|
||||
(set_attr "mode" "HI")
|
||||
(set_attr "unit" "i387")
|
||||
(set_attr "athlon_decode" "vector")
|
||||
(set_attr "amdfam10_decode" "vector")
|
||||
(set_attr "bdver1_decode" "vector")])
|
||||
|
||||
;; Conversion between fixed point and floating point.
|
||||
|
||||
@ -19603,7 +19589,6 @@
|
||||
(define_insn "fnstenv"
|
||||
[(set (match_operand:BLK 0 "memory_operand" "=m")
|
||||
(unspec_volatile:BLK [(const_int 0)] UNSPECV_FNSTENV))
|
||||
(clobber (reg:HI FPCR_REG))
|
||||
(clobber (reg:XF ST0_REG))
|
||||
(clobber (reg:XF ST1_REG))
|
||||
(clobber (reg:XF ST2_REG))
|
||||
@ -19623,7 +19608,6 @@
|
||||
[(unspec_volatile [(match_operand:BLK 0 "memory_operand" "m")]
|
||||
UNSPECV_FLDENV)
|
||||
(clobber (reg:CCFP FPSR_REG))
|
||||
(clobber (reg:HI FPCR_REG))
|
||||
(clobber (reg:XF ST0_REG))
|
||||
(clobber (reg:XF ST1_REG))
|
||||
(clobber (reg:XF ST2_REG))
|
||||
|
||||
@ -1,3 +1,9 @@
|
||||
2018-09-27 Uros Bizjak <ubizjak@gmail.com>
|
||||
|
||||
* gcc.dg/rtl/x86_64/dfinit.c: Update scan-rtl-dump string.
|
||||
* gcc.dg/rtl/x86_64/times-two.c.before-df.c: Ditto.
|
||||
* gcc.target/i386/pr79804.c (foo): Use register "19", not "20".
|
||||
|
||||
2018-09-27 Martin Liska <mliska@suse.cz>
|
||||
|
||||
* g++.dg/pr60518.C: Add -Wno-missing-profile.
|
||||
|
||||
@ -112,5 +112,5 @@ int __RTL (startwith ("no-opt dfinit")) test_1 (int i, int j, int k)
|
||||
frontend, the exit block use of reg 0 (ax) wasn't picked up
|
||||
on, due to not setting up crtl->return_rtx based on
|
||||
DECL_RESULT (fndecl). */
|
||||
/* { dg-final { scan-rtl-dump ";; exit block uses.*0 .ax. 6 .bp. 7 .sp. 20 .frame." "dfinit" } } */
|
||||
/* { dg-final { scan-rtl-dump ";; exit block uses.*0 .ax. 6 .bp. 7 .sp. 19 .frame." "dfinit" } } */
|
||||
/* { dg-final { scan-rtl-dump ";; regs ever live.*0 .ax. 1 .dx. 4 .si. 5 .di. 17 .flags." "dfinit" } } */
|
||||
|
||||
@ -49,6 +49,6 @@ int __RTL (startwith ("rtl-dfinit")) times_two (int i)
|
||||
on, due to not setting up crtl->return_rtx based on
|
||||
DECL_RESULT (fndecl). */
|
||||
|
||||
/* { dg-final { scan-rtl-dump ";; exit block uses.*0 .ax. 6 .bp. 7 .sp. 20 .frame." "dfinit" } } */
|
||||
/* { dg-final { scan-rtl-dump ";; exit block uses.*0 .ax. 6 .bp. 7 .sp. 19 .frame." "dfinit" } } */
|
||||
|
||||
/* { dg-final { scan-rtl-dump ";; regs ever live.*0 .ax. 5 .di. 17 .flags." "dfinit" } } */
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
|
||||
void foo (void)
|
||||
{
|
||||
register int r20 asm ("20");
|
||||
register int r19 asm ("19");
|
||||
|
||||
asm volatile ("# %0" : "=r"(r20)); /* { dg-error "invalid use of register" } */
|
||||
asm volatile ("# %0" : "=r"(r19)); /* { dg-error "invalid use of register" } */
|
||||
} /* { dg-error "cannot be used in asm here" } */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user