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rs6000.md (abssi2_nopower): Convert to define_insn_and_split.
* rs6000.md (abssi2_nopower): Convert to define_insn_and_split.
(nabs_nopower): Same.
(floatdisf2): New pattern.
(absdi2): Convert to define_insn_and_split.
(nabsdi2): Same.
(trunctfsf2): Same.
(floatditf2): Same.
(floatsitf2): Same.
(fix_trunctfdi2): Same.
(fix_trunctfsi2): Same.
From-SVN: r52999
This commit is contained in:
David Edelsohn
David Edelsohn
parent
dda782545e
commit
ea112fc456
@ -1,3 +1,16 @@
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2002-05-01 David Edelsohn <edelsohn@gnu.org>
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* rs6000.md (abssi2_nopower): Convert to define_insn_and_split.
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(nabs_nopower): Same.
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(floatdisf2): New pattern.
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(absdi2): Convert to define_insn_and_split.
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(nabsdi2): Same.
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(trunctfsf2): Same.
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(floatditf2): Same.
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(floatsitf2): Same.
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(fix_trunctfdi2): Same.
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(fix_trunctfsi2): Same.
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2002-05-01 Joseph S. Myers <jsm28@cam.ac.uk>
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* doc/install.texi: Update Texinfo version requirement
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@ -2114,30 +2114,19 @@
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}
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}")
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(define_insn "abssi2_power"
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(define_insn "*abssi2_power"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
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"TARGET_POWER"
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"abs %0,%1")
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(define_insn "abssi2_nopower"
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(define_insn_and_split "abssi2_nopower"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
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(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
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(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
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(clobber (match_scratch:SI 2 "=&r,&r"))]
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"! TARGET_POWER"
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"*
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{
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return (TARGET_POWERPC)
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? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
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: \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
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}"
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[(set_attr "length" "12")])
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(define_split
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[(set (match_operand:SI 0 "gpc_reg_operand" "")
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(abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
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(clobber (match_scratch:SI 2 ""))]
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"! TARGET_POWER && reload_completed"
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"#"
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"&& reload_completed"
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[(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
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(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
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(set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
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@ -2149,24 +2138,13 @@
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"TARGET_POWER"
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"nabs %0,%1")
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(define_insn "*nabs_no_power"
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(define_insn_and_split "*nabs_nopower"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
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(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
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(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
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(clobber (match_scratch:SI 2 "=&r,&r"))]
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"! TARGET_POWER"
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"*
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{
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return (TARGET_POWERPC)
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? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
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: \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
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}"
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[(set_attr "length" "12")])
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(define_split
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[(set (match_operand:SI 0 "gpc_reg_operand" "")
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(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))))
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(clobber (match_scratch:SI 2 ""))]
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"! TARGET_POWER && reload_completed"
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"#"
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"&& reload_completed"
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[(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
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(set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
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(set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
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@ -5462,6 +5440,20 @@
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"TARGET_POWERPC64 && TARGET_HARD_FLOAT"
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"fctidz %0,%1"
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[(set_attr "type" "fp")])
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;; This only is safe if rounding mode set appropriately.
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(define_insn_and_split "floatdisf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(float:SF (match_operand:DI 1 "gpc_reg_operand" "f")))
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(clobber (match_scratch:DF 2 "=f"))]
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"TARGET_POWERPC64 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
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"#"
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"&& reload_completed"
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[(set (match_dup 2)
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(float:DF (match_dup 1)))
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(set (match_dup 0)
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(float_truncate:SF (match_dup 2)))]
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"")
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;; Define the DImode operations that can be done in a small number
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;; of instructions. The & constraints are to prevent the register
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@ -6070,37 +6062,25 @@
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}
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}")
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(define_insn "absdi2"
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(define_insn_and_split "absdi2"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
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(abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
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(abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
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(clobber (match_scratch:DI 2 "=&r,&r"))]
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"TARGET_POWERPC64"
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"sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0"
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[(set_attr "length" "12")])
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(define_split
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[(set (match_operand:DI 0 "gpc_reg_operand" "")
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(abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
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(clobber (match_scratch:DI 2 ""))]
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"TARGET_POWERPC64 && reload_completed"
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"#"
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"&& reload_completed"
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[(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
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(set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
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(set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
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"")
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(define_insn "*nabsdi2"
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(define_insn_and_split "*nabsdi2"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
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(neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
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(neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
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(clobber (match_scratch:DI 2 "=&r,&r"))]
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"TARGET_POWERPC64"
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"sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2"
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[(set_attr "length" "12")])
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(define_split
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[(set (match_operand:DI 0 "gpc_reg_operand" "")
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(neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))))
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(clobber (match_scratch:DI 2 ""))]
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"TARGET_POWERPC64 && reload_completed"
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"#"
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"&& reload_completed"
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[(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
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(set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
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(set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
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@ -8207,52 +8187,68 @@
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(define_insn_and_split "trunctfsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))]
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(float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
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(clobber (match_scratch:DF 2 "=f"))]
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"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
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"#"
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""
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"&& reload_completed"
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[(set (match_dup 2)
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(float_truncate:DF (match_dup 1)))
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(set (match_dup 0)
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(float_truncate:SF (match_dup 2)))]
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"
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{
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operands[2] = gen_reg_rtx (DFmode);
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}")
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"")
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(define_expand "floatditf2"
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(define_insn_and_split "floatditf2"
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[(set (match_operand:TF 0 "gpc_reg_operand" "=f")
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(float:TF (match_operand:DI 1 "gpc_reg_operand" "f")))
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(clobber (match_scratch:DF 2 "=f"))]
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"DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
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&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
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"#"
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"&& reload_completed"
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[(set (match_dup 2)
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(float:DF (match_operand:DI 1 "gpc_reg_operand" "")))
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(set (match_operand:TF 0 "gpc_reg_operand" "")
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(float_extend:TF (match_dup 2)))]
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"DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
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&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
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"{ operands[2] = gen_reg_rtx (DFmode); }")
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"")
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(define_expand "floatsitf2"
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(define_insn_and_split "floatsitf2"
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[(set (match_operand:TF 0 "gpc_reg_operand" "=f")
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(float:TF (match_operand:SI 1 "gpc_reg_operand" "f")))
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(clobber (match_scratch:DF 2 "=f"))]
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"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
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"#"
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"&& reload_completed"
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[(set (match_dup 2)
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(float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
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(set (match_operand:TF 0 "gpc_reg_operand" "")
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(float_extend:TF (match_dup 2)))]
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"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
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"{ operands[2] = gen_reg_rtx (DFmode); }")
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"")
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(define_expand "fix_trunctfdi2"
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(define_insn_and_split "fix_trunctfdi2"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=f")
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(fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))]
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"DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
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&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
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"#"
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"&& reload_completed"
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[(set (match_dup 2)
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(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
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(set (match_operand:DI 0 "gpc_reg_operand" "")
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(fix:SI (match_dup 2)))]
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"DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
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&& TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
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"{ operands[2] = gen_reg_rtx (DFmode); }")
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"")
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(define_expand "fix_trunctfsi2"
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(define_insn_and_split "fix_trunctfsi2"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=f")
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(fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))]
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"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
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"#"
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"&& reload_completed"
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[(set (match_dup 2)
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(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(fix:SI (match_dup 2)))]
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"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128"
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"{ operands[2] = gen_reg_rtx (DFmode); }")
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"")
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(define_insn "negtf2"
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[(set (match_operand:TF 0 "gpc_reg_operand" "=f")
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