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aarch64: Reimplement most vpadal intrinsics using builtins
This patch reimplements most of the vpadal intrinsics to use RTL builtins in the normal way. The ones that aren't converted are the int32x2_t -> int64x1_t ones as the RTL pattern doesn't currently handle these modes. We don't have a V1DI mode so it would need to return a DImode value or a V2DI one with the first lane being the result. It's not hard to do, but it would require a bit more refactoring so we can do it separately later. This patch hopefully improves the status quo. The new Vwhalf mode attribute is created because the existing Vwtype attribute maps V8QI wrongly (for this pattern) to "8h" as the suffix rather than "4h" as needed. gcc/ * config/aarch64/iterators.md (Vwhalf): New iterator. * config/aarch64/aarch64-simd.md (aarch64_<sur>adalp<mode>_3): Rename to... (aarch64_<sur>adalp<mode>): ... This. Make more builtin-friendly. (<sur>sadv16qi): Adjust callsite of the above. * config/aarch64/aarch64-simd-builtins.def (sadalp, uadalp): New builtins. * config/aarch64/arm_neon.h (vpadal_s8): Reimplement using builtins. (vpadal_s16): Likewise. (vpadal_u8): Likewise. (vpadal_u16): Likewise. (vpadalq_s8): Likewise. (vpadalq_s16): Likewise. (vpadalq_s32): Likewise. (vpadalq_u8): Likewise. (vpadalq_u16): Likewise. (vpadalq_u32): Likewise.
This commit is contained in:
Kyrylo Tkachov
parent
79db5945ad
commit
e811f10b61
@ -157,6 +157,9 @@
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BUILTIN_VDQ_BHSI (TERNOP, saba, 0, NONE)
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BUILTIN_VDQ_BHSI (TERNOPU, uaba, 0, NONE)
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BUILTIN_VDQV_S (BINOP, sadalp, 0, NONE)
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BUILTIN_VDQV_S (BINOPU, uadalp, 0, NONE)
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/* Implemented by aarch64_<sur><addsub>hn<mode>. */
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BUILTIN_VQN (BINOP, addhn, 0, NONE)
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BUILTIN_VQN (BINOP, subhn, 0, NONE)
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@ -801,13 +801,13 @@
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[(set_attr "type" "neon_arith_acc<q>")]
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)
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(define_insn "aarch64_<sur>adalp<mode>_3"
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(define_insn "aarch64_<sur>adalp<mode>"
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[(set (match_operand:<VDBLW> 0 "register_operand" "=w")
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(unspec:<VDBLW> [(match_operand:VDQV_S 1 "register_operand" "w")
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(match_operand:<VDBLW> 2 "register_operand" "0")]
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(unspec:<VDBLW> [(match_operand:VDQV_S 2 "register_operand" "w")
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(match_operand:<VDBLW> 1 "register_operand" "0")]
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ADALP))]
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"TARGET_SIMD"
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"<sur>adalp\t%0.<Vwtype>, %1.<Vtype>"
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"<sur>adalp\t%0.<Vwhalf>, %2.<Vtype>"
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[(set_attr "type" "neon_reduc_add<q>")]
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)
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@ -852,8 +852,7 @@
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operands[2]));
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emit_insn (gen_aarch64_<sur>abalv16qi_4 (reduc, operands[1],
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operands[2], reduc));
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emit_insn (gen_aarch64_<sur>adalpv8hi_3 (operands[3], reduc,
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operands[3]));
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emit_insn (gen_aarch64_<sur>adalpv8hi (operands[3], operands[3], reduc));
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emit_move_insn (operands[0], operands[3]);
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DONE;
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}
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@ -9289,24 +9289,14 @@ __extension__ extern __inline int16x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vpadal_s8 (int16x4_t __a, int8x8_t __b)
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{
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int16x4_t __result;
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__asm__ ("sadalp %0.4h,%2.8b"
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: "=w"(__result)
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: "0"(__a), "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_sadalpv8qi (__a, __b);
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}
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__extension__ extern __inline int32x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vpadal_s16 (int32x2_t __a, int16x4_t __b)
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{
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int32x2_t __result;
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__asm__ ("sadalp %0.2s,%2.4h"
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: "=w"(__result)
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: "0"(__a), "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_sadalpv4hi (__a, __b);
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}
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__extension__ extern __inline int64x1_t
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@ -9325,24 +9315,14 @@ __extension__ extern __inline uint16x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vpadal_u8 (uint16x4_t __a, uint8x8_t __b)
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{
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uint16x4_t __result;
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__asm__ ("uadalp %0.4h,%2.8b"
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: "=w"(__result)
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: "0"(__a), "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_uadalpv8qi_uuu (__a, __b);
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}
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__extension__ extern __inline uint32x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vpadal_u16 (uint32x2_t __a, uint16x4_t __b)
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{
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uint32x2_t __result;
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__asm__ ("uadalp %0.2s,%2.4h"
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: "=w"(__result)
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: "0"(__a), "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_uadalpv4hi_uuu (__a, __b);
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}
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__extension__ extern __inline uint64x1_t
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@ -9361,72 +9341,42 @@ __extension__ extern __inline int16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vpadalq_s8 (int16x8_t __a, int8x16_t __b)
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{
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int16x8_t __result;
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__asm__ ("sadalp %0.8h,%2.16b"
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: "=w"(__result)
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: "0"(__a), "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_sadalpv16qi (__a, __b);
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}
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__extension__ extern __inline int32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vpadalq_s16 (int32x4_t __a, int16x8_t __b)
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{
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int32x4_t __result;
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__asm__ ("sadalp %0.4s,%2.8h"
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: "=w"(__result)
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: "0"(__a), "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_sadalpv8hi (__a, __b);
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}
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__extension__ extern __inline int64x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vpadalq_s32 (int64x2_t __a, int32x4_t __b)
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{
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int64x2_t __result;
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__asm__ ("sadalp %0.2d,%2.4s"
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: "=w"(__result)
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: "0"(__a), "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_sadalpv4si (__a, __b);
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}
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__extension__ extern __inline uint16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vpadalq_u8 (uint16x8_t __a, uint8x16_t __b)
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{
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uint16x8_t __result;
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__asm__ ("uadalp %0.8h,%2.16b"
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: "=w"(__result)
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: "0"(__a), "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_uadalpv16qi_uuu (__a, __b);
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}
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__extension__ extern __inline uint32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vpadalq_u16 (uint32x4_t __a, uint16x8_t __b)
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{
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uint32x4_t __result;
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__asm__ ("uadalp %0.4s,%2.8h"
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: "=w"(__result)
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: "0"(__a), "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_uadalpv8hi_uuu (__a, __b);
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}
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__extension__ extern __inline uint64x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vpadalq_u32 (uint64x2_t __a, uint32x4_t __b)
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{
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uint64x2_t __result;
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__asm__ ("uadalp %0.2d,%2.4s"
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: "=w"(__result)
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: "0"(__a), "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_uadalpv4si_uuu (__a, __b);
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}
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__extension__ extern __inline int16x4_t
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@ -1291,6 +1291,11 @@
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(V8HI "4s") (V4SI "2d")
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(V8HF "4s") (V4SF "2d")])
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;; Widened mode with half the element register suffixes for VD_BHSI/VQW/VQ_HSF.
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(define_mode_attr Vwhalf [(V8QI "4h") (V4HI "2s")
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(V2SI "1d") (V16QI "8h")
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(V8HI "4s") (V4SI "2d")])
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;; SVE vector after narrowing.
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(define_mode_attr Ventype [(VNx8HI "b")
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(VNx4SI "h") (VNx4SF "h")
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