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rs6000: Improve isel
This removes output_isel. Instead, the define_insn's now output the isel instructions directly. It adds a reg_or_zero operand predicate, too, because the reg_or_cint predicate is too lax here. Also use it in the "reversed" variants of the instructions. * config/rs6000/predicates.md (zero_constant, all_ones_constant): Move up in file. (reg_or_cint_operand): Fix comment. (reg_or_zero_operand): New predicate. * config/rs6000/rs6000-protos.h (output_isel): Delete. * config/rs6000/rs6000.c (output_isel): Delete. * config/rs6000/rs6000.md (isel_signed_<mode>): Use reg_or_zero_operand instead of reg_or_cint_operand. Output instruction directly (not via output_isel). (isel_unsigned_<mode>): Ditto. (*isel_reversed_signed_<mode>): Use reg_or_zero_operand instead of gpc_reg_operand. Add an instruction alternative for this. Output instruction directly. (*isel_reversed_unsigned_<mode>): Ditto. From-SVN: r253665
This commit is contained in:
Segher Boessenkool
Segher Boessenkool
parent
3ff1b2b0a9
commit
e7d77cf92d
@ -1,3 +1,20 @@
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2017-10-11 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/predicates.md (zero_constant, all_ones_constant):
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Move up in file.
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(reg_or_cint_operand): Fix comment.
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(reg_or_zero_operand): New predicate.
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* config/rs6000/rs6000-protos.h (output_isel): Delete.
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* config/rs6000/rs6000.c (output_isel): Delete.
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* config/rs6000/rs6000.md (isel_signed_<mode>): Use reg_or_zero_operand
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instead of reg_or_cint_operand. Output instruction directly (not via
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output_isel).
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(isel_unsigned_<mode>): Ditto.
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(*isel_reversed_signed_<mode>): Use reg_or_zero_operand instead of
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gpc_reg_operand. Add an instruction alternative for this. Output
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instruction directly.
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(*isel_reversed_unsigned_<mode>): Ditto.
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2017-10-11 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.c (ix86_canonicalize_comparison): New function.
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@ -199,6 +199,16 @@
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return CA_REGNO_P (REGNO (op));
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})
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;; Return 1 if operand is constant zero (scalars and vectors).
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(define_predicate "zero_constant"
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(and (match_code "const_int,const_double,const_wide_int,const_vector")
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(match_test "op == CONST0_RTX (mode)")))
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;; Return 1 if operand is constant -1 (scalars and vectors).
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(define_predicate "all_ones_constant"
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(and (match_code "const_int,const_double,const_wide_int,const_vector")
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(match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)")))
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;; Return 1 if op is a signed 5-bit constant integer.
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(define_predicate "s5bit_cint_operand"
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(and (match_code "const_int")
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@ -543,12 +553,16 @@
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(match_operand 0 "u_short_cint_operand")
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(match_operand 0 "gpc_reg_operand")))
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;; Return 1 if op is any constant integer
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;; or non-special register.
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;; Return 1 if op is any constant integer or a non-special register.
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(define_predicate "reg_or_cint_operand"
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(ior (match_code "const_int")
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(match_operand 0 "gpc_reg_operand")))
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;; Return 1 if op is constant zero or a non-special register.
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(define_predicate "reg_or_zero_operand"
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(ior (match_operand 0 "zero_constant")
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(match_operand 0 "gpc_reg_operand")))
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;; Return 1 if op is a constant integer valid for addition with addis, addi.
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(define_predicate "add_cint_operand"
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(and (match_code "const_int")
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@ -744,16 +758,6 @@
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(and (match_test "easy_altivec_constant (op, mode)")
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(match_test "vspltis_shifted (op) != 0")))))
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;; Return 1 if operand is constant zero (scalars and vectors).
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(define_predicate "zero_constant"
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(and (match_code "const_int,const_double,const_wide_int,const_vector")
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(match_test "op == CONST0_RTX (mode)")))
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;; Return 1 if operand is constant -1 (scalars and vectors).
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(define_predicate "all_ones_constant"
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(and (match_code "const_int,const_double,const_wide_int,const_vector")
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(match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)")))
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;; Return 1 if operand is a vector int register or is either a vector constant
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;; of all 0 bits of a vector constant of all 1 bits.
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(define_predicate "vector_int_reg_or_same_bit"
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@ -209,7 +209,6 @@ extern void rs6000_emit_epilogue (int);
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extern void rs6000_expand_split_stack_prologue (void);
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extern void rs6000_split_stack_space_check (rtx, rtx);
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extern void rs6000_emit_eh_reg_restore (rtx, rtx);
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extern const char * output_isel (rtx *);
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extern void rs6000_call_aix (rtx, rtx, rtx, rtx);
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extern void rs6000_sibcall_aix (rtx, rtx, rtx, rtx);
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extern void rs6000_aix_asm_output_dwarf_table_ref (char *);
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@ -23255,24 +23255,6 @@ rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
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return 1;
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}
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const char *
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output_isel (rtx *operands)
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{
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enum rtx_code code;
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code = GET_CODE (operands[1]);
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if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
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{
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gcc_assert (GET_CODE (operands[2]) == REG
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&& GET_CODE (operands[3]) == REG);
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PUT_CODE (operands[1], reverse_condition (code));
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return "isel %0,%3,%2,%j1";
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}
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return "isel %0,%2,%3,%j1";
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}
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void
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rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
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{
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@ -4938,13 +4938,11 @@
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(match_operator 1 "scc_comparison_operator"
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[(match_operand:CC 4 "cc_reg_operand" "y,y")
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(const_int 0)])
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(match_operand:GPR 2 "reg_or_cint_operand" "O,b")
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(match_operand:GPR 2 "reg_or_zero_operand" "O,b")
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(match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
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"TARGET_ISEL<sel>"
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"*
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{ return output_isel (operands); }"
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[(set_attr "type" "isel")
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(set_attr "length" "4")])
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"isel %0,%2,%3,%j1"
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[(set_attr "type" "isel")])
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(define_insn "isel_unsigned_<mode>"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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@ -4952,45 +4950,45 @@
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(match_operator 1 "scc_comparison_operator"
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[(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
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(const_int 0)])
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(match_operand:GPR 2 "reg_or_cint_operand" "O,b")
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(match_operand:GPR 2 "reg_or_zero_operand" "O,b")
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(match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
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"TARGET_ISEL<sel>"
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"*
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{ return output_isel (operands); }"
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[(set_attr "type" "isel")
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(set_attr "length" "4")])
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"isel %0,%2,%3,%j1"
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[(set_attr "type" "isel")])
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;; These patterns can be useful for combine; they let combine know that
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;; isel can handle reversed comparisons so long as the operands are
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;; registers.
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(define_insn "*isel_reversed_signed_<mode>"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(if_then_else:GPR
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(match_operator 1 "scc_rev_comparison_operator"
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[(match_operand:CC 4 "cc_reg_operand" "y")
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[(match_operand:CC 4 "cc_reg_operand" "y,y")
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(const_int 0)])
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(match_operand:GPR 2 "gpc_reg_operand" "b")
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(match_operand:GPR 3 "gpc_reg_operand" "b")))]
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(match_operand:GPR 2 "gpc_reg_operand" "r,r")
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(match_operand:GPR 3 "reg_or_zero_operand" "O,b")))]
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"TARGET_ISEL<sel>"
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"*
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{ return output_isel (operands); }"
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[(set_attr "type" "isel")
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(set_attr "length" "4")])
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{
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PUT_CODE (operands[1], reverse_condition (GET_CODE (operands[1])));
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return "isel %0,%3,%2,%j1";
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}
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[(set_attr "type" "isel")])
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(define_insn "*isel_reversed_unsigned_<mode>"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(if_then_else:GPR
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(match_operator 1 "scc_rev_comparison_operator"
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[(match_operand:CCUNS 4 "cc_reg_operand" "y")
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[(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
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(const_int 0)])
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(match_operand:GPR 2 "gpc_reg_operand" "b")
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(match_operand:GPR 3 "gpc_reg_operand" "b")))]
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(match_operand:GPR 2 "gpc_reg_operand" "r,r")
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(match_operand:GPR 3 "reg_or_zero_operand" "O,b")))]
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"TARGET_ISEL<sel>"
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"*
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{ return output_isel (operands); }"
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[(set_attr "type" "isel")
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(set_attr "length" "4")])
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{
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PUT_CODE (operands[1], reverse_condition (GET_CODE (operands[1])));
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return "isel %0,%3,%2,%j1";
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}
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[(set_attr "type" "isel")])
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;; Floating point conditional move
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(define_expand "mov<mode>cc"
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