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sse.md ("mov<mode>_internal"): Use <sseinsnmode> mode attribute for TARGET_AVX512VL.
/gcc
* config/i386/sse.md ("mov<mode>_internal"): Use <sseinsnmode>
mode attribute for TARGET_AVX512VL.
* config/i386/i386.opt (mprefer-avx256): New option.
* config/i386/i386.c (ix86_target_string): Add -mprefer-avx256
to flag_opts.
(ix86_preferred_simd_mode): Return 256-bit AVX modes
for TARGET_PREFER_AVX256.
* doc/invoke.texi (x86 Options): Document -mprefer-avx256.
/testsuite
* gcc.target/i386/avx512f-constant-set.c: New test.
* g++.dg/ext/pr57362.C: Test __attribute__((target("prefer-avx256"))).
* gcc.target/i386/avx512f-prefer.c: New test.
From-SVN: r253089
This commit is contained in:
Sergey Shalnov
Uros Bizjak
parent
b9327b5ac2
commit
e7ba6a6041
@ -1,3 +1,17 @@
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2017-09-22 Sergey Shalnov <sergey.shalnov@intel.com>
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* config/i386/sse.md ("mov<mode>_internal"): Use <sseinsnmode>
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mode attribute for TARGET_AVX512VL.
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2017-09-21 Sergey Shalnov <sergey.shalnov@intel.com>
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* config/i386/i386.opt (mprefer-avx256): New option.
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* config/i386/i386.c (ix86_target_string): Add -mprefer-avx256
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to flag_opts.
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(ix86_preferred_simd_mode): Return 256-bit AVX modes
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for TARGET_PREFER_AVX256.
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* doc/invoke.texi (x86 Options): Document -mprefer-avx256.
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2017-09-21 Jeff Law <law@redhat.com>
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* config/i386/i386.c (ix86_adjust_stack_and_probe_stack_clash):
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@ -4751,6 +4751,7 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2,
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{ "-mavx256-split-unaligned-load", MASK_AVX256_SPLIT_UNALIGNED_LOAD },
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{ "-mavx256-split-unaligned-store", MASK_AVX256_SPLIT_UNALIGNED_STORE },
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{ "-mprefer-avx128", MASK_PREFER_AVX128 },
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{ "-mprefer-avx256", MASK_PREFER_AVX256 },
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{ "-mcall-ms2sysv-xlogues", MASK_CALL_MS2SYSV_XLOGUES }
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};
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@ -51848,20 +51849,39 @@ ix86_preferred_simd_mode (scalar_mode mode)
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switch (mode)
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{
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case E_QImode:
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return TARGET_AVX512BW ? V64QImode :
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(TARGET_AVX && !TARGET_PREFER_AVX128) ? V32QImode : V16QImode;
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if (TARGET_AVX512BW && !TARGET_PREFER_AVX256)
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return V64QImode;
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else if (TARGET_AVX && !TARGET_PREFER_AVX128)
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return V32QImode;
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else
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return V16QImode;
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case E_HImode:
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return TARGET_AVX512BW ? V32HImode :
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(TARGET_AVX && !TARGET_PREFER_AVX128) ? V16HImode : V8HImode;
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if (TARGET_AVX512BW && !TARGET_PREFER_AVX256)
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return V32HImode;
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else if (TARGET_AVX && !TARGET_PREFER_AVX128)
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return V16HImode;
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else
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return V8HImode;
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case E_SImode:
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return TARGET_AVX512F ? V16SImode :
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(TARGET_AVX && !TARGET_PREFER_AVX128) ? V8SImode : V4SImode;
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if (TARGET_AVX512F && !TARGET_PREFER_AVX256)
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return V16SImode;
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else if (TARGET_AVX && !TARGET_PREFER_AVX128)
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return V8SImode;
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else
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return V4SImode;
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case E_DImode:
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return TARGET_AVX512F ? V8DImode :
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(TARGET_AVX && !TARGET_PREFER_AVX128) ? V4DImode : V2DImode;
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if (TARGET_AVX512F && !TARGET_PREFER_AVX256)
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return V8DImode;
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else if (TARGET_AVX && !TARGET_PREFER_AVX128)
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return V4DImode;
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else
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return V2DImode;
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case E_SFmode:
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if (TARGET_AVX512F)
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if (TARGET_AVX512F && !TARGET_PREFER_AVX256)
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return V16SFmode;
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else if (TARGET_AVX && !TARGET_PREFER_AVX128)
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return V8SFmode;
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@ -51869,7 +51889,7 @@ ix86_preferred_simd_mode (scalar_mode mode)
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return V4SFmode;
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case E_DFmode:
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if (TARGET_AVX512F)
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if (TARGET_AVX512F && !TARGET_PREFER_AVX256)
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return V8DFmode;
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else if (TARGET_AVX && !TARGET_PREFER_AVX128)
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return V4DFmode;
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@ -51889,8 +51909,14 @@ ix86_preferred_simd_mode (scalar_mode mode)
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static unsigned int
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ix86_autovectorize_vector_sizes (void)
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{
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return TARGET_AVX512F ? 64 | 32 | 16 :
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(TARGET_AVX && !TARGET_PREFER_AVX128) ? 32 | 16 : 0;
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unsigned int bytesizes = 0;
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if (TARGET_AVX512F && !TARGET_PREFER_AVX256)
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bytesizes |= (64 | 32 | 16);
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else if (TARGET_AVX && !TARGET_PREFER_AVX128)
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bytesizes |= (32 | 16);
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return bytesizes;
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}
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/* Implemenation of targetm.vectorize.get_mask_mode. */
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@ -588,9 +588,13 @@ Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4
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or znver1 and Haifa scheduling is selected.
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mprefer-avx128
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Target Report Mask(PREFER_AVX128) SAVE
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Target Report Mask(PREFER_AVX128) Save
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Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
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mprefer-avx256
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Target Report Mask(PREFER_AVX256) Save
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Use 256-bit AVX instructions instead of 512-bit AVX instructions in the auto-vectorizer.
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;; ISA support
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m32
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@ -978,7 +978,7 @@
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(set (attr "mode")
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(cond [(and (eq_attr "alternative" "1")
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(match_test "TARGET_AVX512VL"))
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(const_string "XI")
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(const_string "<sseinsnmode>")
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(and (match_test "<MODE_SIZE> == 16")
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(ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL")
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(and (eq_attr "alternative" "3")
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@ -1194,7 +1194,7 @@ See RS/6000 and PowerPC Options.
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-mincoming-stack-boundary=@var{num} @gol
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-mcld -mcx16 -msahf -mmovbe -mcrc32 @gol
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-mrecip -mrecip=@var{opt} @gol
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-mvzeroupper -mprefer-avx128 @gol
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-mvzeroupper -mprefer-avx128 -mprefer-avx256 @gol
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-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol
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-mavx2 -mavx512f -mavx512pf -mavx512er -mavx512cd -mavx512vl @gol
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-mavx512bw -mavx512dq -mavx512ifma -mavx512vbmi -msha -maes @gol
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@ -25858,6 +25858,11 @@ intrinsics.
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This option instructs GCC to use 128-bit AVX instructions instead of
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256-bit AVX instructions in the auto-vectorizer.
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@item -mprefer-avx256
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@opindex mprefer-avx256
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This option instructs GCC to use 256-bit AVX instructions instead of
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512-bit AVX instructions in the auto-vectorizer.
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@item -mcx16
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@opindex mcx16
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This option enables GCC to generate @code{CMPXCHG16B} instructions in 64-bit
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@ -1,3 +1,12 @@
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2017-09-22 Sergey Shalnov <sergey.shalnov@intel.com>
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* gcc.target/i386/avx512f-constant-set.c: New test.
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2017-09-21 Sergey Shalnov <sergey.shalnov@intel.com>
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* g++.dg/ext/pr57362.C: Test __attribute__((target("prefer-avx256"))).
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* gcc.target/i386/avx512f-prefer.c: New test.
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2017-09-21 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
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* lib/target-supports.exp
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@ -81,6 +81,8 @@ __attribute__((target("dispatch-scheduler")))
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int foo(void) { return 1; }
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__attribute__((target("prefer-avx128")))
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int foo(void) { return 1; }
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__attribute__((target("prefer-avx256")))
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int foo(void) { return 1; }
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__attribute__((target("32")))
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int foo(void) { return 1; }
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__attribute__((target("64")))
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11
gcc/testsuite/gcc.target/i386/avx512f-constant-set.c
Normal file
11
gcc/testsuite/gcc.target/i386/avx512f-constant-set.c
Normal file
@ -0,0 +1,11 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -march=skylake-avx512" } */
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/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
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void
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avx512f_test (short *table)
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{
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int i;
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for (i = 0; i < 128; ++i)
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table[i] = -1;
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}
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18
gcc/testsuite/gcc.target/i386/avx512f-prefer.c
Normal file
18
gcc/testsuite/gcc.target/i386/avx512f-prefer.c
Normal file
@ -0,0 +1,18 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -march=skylake-avx512 -mprefer-avx256" } */
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/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
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/* { dg-final { scan-assembler "vmulpd" } } */
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#define N 1024
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double a[N], b[N], c[N];
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void
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avx512f_test (void)
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{
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int i;
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for (i = 0; i < N; i++)
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c[i] = a[i] * b[i];
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}
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