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(rot[lr][shq]i3): Allow 'N', 'O' or 'P' operands.
From-SVN: r13524
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@ -64,6 +64,9 @@
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;;- 'K' all integers EXCEPT -128 .. 127
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;;- 'L' -8 .. -1
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;;- 'M' all integers EXCEPT -256 .. 255
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;;- 'N' 24 .. 31
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;;- 'O' 16
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;;- 'P' 8 .. 15
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;;- Assembler specs:
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;;- "%." size separator ("." or "") move%.l d0,d1
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@ -4712,38 +4715,84 @@
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(define_insn "rotlsi3"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(rotate:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "general_operand" "dI")))]
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(match_operand:SI 2 "general_operand" "dINO")))]
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"!TARGET_5200"
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"rol%.l %2,%0")
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"*
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{
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if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
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return \"swap %0\";
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else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
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{
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INTVAL (operands[2]) = 32 - INTVAL (operands[2]);
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return \"ror%.l %2,%0\";
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}
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else
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return \"rol%.l %2,%0\";
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}")
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(define_insn "rotlhi3"
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[(set (match_operand:HI 0 "register_operand" "=d")
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(rotate:HI (match_operand:HI 1 "register_operand" "0")
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(match_operand:HI 2 "general_operand" "dI")))]
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(match_operand:HI 2 "general_operand" "dIP")))]
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"!TARGET_5200"
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"rol%.w %2,%0")
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"*
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{
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if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
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{
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INTVAL (operands[2]) = 16 - INTVAL (operands[2]);
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return \"ror%.w %2,%0\";
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}
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else
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return \"rol%.w %2,%0\";
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}")
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(define_insn ""
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[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
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(rotate:HI (match_dup 0)
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(match_operand:HI 1 "general_operand" "dI")))]
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(match_operand:HI 1 "general_operand" "dIP")))]
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"!TARGET_5200"
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"rol%.w %1,%0")
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"*
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{
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if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
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{
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INTVAL (operands[2]) = 16 - INTVAL (operands[2]);
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return \"ror%.w %2,%0\";
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}
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else
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return \"rol%.w %2,%0\";
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}")
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(define_insn "rotlqi3"
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[(set (match_operand:QI 0 "register_operand" "=d")
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(rotate:QI (match_operand:QI 1 "register_operand" "0")
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(match_operand:QI 2 "general_operand" "dI")))]
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"!TARGET_5200"
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"rol%.b %2,%0")
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"*
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{
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if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
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{
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INTVAL (operands[2]) = 8 - INTVAL (operands[2]);
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return \"ror%.b %2,%0\";
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}
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else
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return \"rol%.b %2,%0\";
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}")
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(define_insn ""
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[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
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(rotate:QI (match_dup 0)
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(match_operand:QI 1 "general_operand" "dI")))]
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"!TARGET_5200"
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"rol%.b %1,%0")
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"*
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{
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if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
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{
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INTVAL (operands[2]) = 8 - INTVAL (operands[2]);
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return \"ror%.b %2,%0\";
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}
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else
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return \"rol%.b %2,%0\";
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}")
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(define_insn "rotrsi3"
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[(set (match_operand:SI 0 "register_operand" "=d")
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