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({MASK,TARGET}_{OPEN_VMS,FLOAT_VAX}): New macros.
(TARGET_SWITCHES): Add float-vax and float-ieee. ({FUNCTION,LIBCALL}_VALUE, FUNCTION_VALUE_REGNO_P): R1 and R33 are also return registers. (ASM_OUTPUT_DOUBLE): Support both floating-point formats. (PRINT_OPERAND_FUNCT_VALID_P): Add ',' and '-'. From-SVN: r13184
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@ -162,6 +162,17 @@ extern enum alpha_fp_trap_mode alpha_fptm;
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#define MASK_BYTE_OPS 256
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#define TARGET_BYTE_OPS (target_flags & MASK_BYTE_OPS)
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/* This means we are compiling for openVMS. */
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#define MASK_OPEN_VMS 256
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#define TARGET_OPEN_VMS (target_flags & MASK_OPEN_VMS)
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/* This means we handle floating points in VAX F- (float)
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or G- (double) Format. */
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#define MASK_FLOAT_VAX 512
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#define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
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/* Macro to define tables used to set the flags.
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This is a list in braces of pairs in braces,
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each pair being { "NAME", VALUE }
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@ -179,6 +190,8 @@ extern enum alpha_fp_trap_mode alpha_fptm;
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{"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT}, \
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{"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT}, \
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{"build-constants", MASK_BUILD_CONSTANTS}, \
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{"float-vax", MASK_FLOAT_VAX}, \
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{"float-ieee", -MASK_FLOAT_VAX}, \
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{"byte", MASK_BYTE_OPS}, \
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{"", TARGET_DEFAULT | TARGET_CPU_DEFAULT} }
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@ -846,18 +859,24 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
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$f0 for floating-point functions. */
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#define FUNCTION_VALUE(VALTYPE, FUNC) \
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gen_rtx (REG, \
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(INTEGRAL_MODE_P (TYPE_MODE (VALTYPE)) \
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&& TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
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? word_mode : TYPE_MODE (VALTYPE), \
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TARGET_FPREGS && TREE_CODE (VALTYPE) == REAL_TYPE ? 32 : 0)
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gen_rtx (REG, \
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(INTEGRAL_MODE_P (TYPE_MODE (VALTYPE)) \
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&& TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
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? word_mode : TYPE_MODE (VALTYPE), \
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((TARGET_FPREGS \
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&& (TREE_CODE (VALTYPE) == REAL_TYPE \
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|| TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \
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? 32 : 0))
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/* Define how to find the value returned by a library function
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assuming the value has mode MODE. */
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#define LIBCALL_VALUE(MODE) \
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gen_rtx (REG, MODE, \
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TARGET_FPREGS && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 0)
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gen_rtx (REG, MODE, \
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(TARGET_FPREGS \
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&& (GET_MODE_CLASS (MODE) == MODE_FLOAT \
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|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
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? 32 : 0))
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/* The definition of this macro implies that there are cases where
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a scalar value cannot be returned in registers.
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@ -872,7 +891,8 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
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/* 1 if N is a possible register number for a function value
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as seen by the caller. */
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#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 32)
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#define FUNCTION_VALUE_REGNO_P(N) \
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((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
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/* 1 if N is a possible register number for function argument passing.
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On Alpha, these are $16-$21 and $f16-$f21. */
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@ -1028,6 +1048,11 @@ extern struct rtx_def *alpha_builtin_saveregs ();
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extern struct rtx_def *alpha_compare_op0, *alpha_compare_op1;
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extern int alpha_compare_fp_p;
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/* Make (or fake) .linkage entry for function call.
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IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
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extern void alpha_need_linkage ();
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/* This macro produces the initial definition of a function name. On the
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Alpha, we need to save the function name for the prologue and epilogue. */
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@ -1812,7 +1837,7 @@ literal_section () \
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{ \
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char str[30]; \
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REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str); \
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fprintf (FILE, "\t.t_floating %s\n", str); \
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fprintf (FILE, "\t.%c_floating %s\n", (TARGET_FLOAT_VAX)?'g':'t', str); \
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} \
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}
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@ -2004,10 +2029,17 @@ literal_section () \
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+ Generates trap-mode suffix for instructions that accept the
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sui suffix (cvtqt and cvtqs).
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, Generates single precision suffix for floating point
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instructions (s for IEEE, f for VAX)
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- Generates double precision suffix for floating point
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instructions (t for IEEE, g for VAX)
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*/
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#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
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((CODE) == '&' || (CODE) == '\'' || (CODE) == ')' || (CODE) == '+')
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((CODE) == '&' || (CODE) == '\'' || (CODE) == ')' || (CODE) == '+' \
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|| (CODE) == ',' || (CODE) == '-')
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/* Print a memory address as an operand to reference that memory location. */
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