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mips.md (reload_outsi): Added missing REGNO call.
* mips.md (reload_outsi): Added missing REGNO call. (smulsi3_highpart, umulsi3_highpart): Provide prototype for function pointer. (mul_acc_di, mul_acc_64bit_di): Don't use match_op_dup, use another match_operator and compare the codes. * mips.h (MASK_DEBUG_E, MASK_DEBUG_I): Set to zero. * MIPS multiply pattern fixes: * mips.h (enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS): Add union classes for HI, LO, or HILO plus general registers. (GENERATE_MADD): Deleted. * mips.md (mulsi3_mult3): Don't disparage output-LO alternative. Add TARGET_MAD to condition. (mulsi3): Test HAVE_mulsi3_mult3, not specific flags. (mul_acc_si): Expand GENERATE_MADD here; it's the only use. Use "*d" for accumulator, to give preference to LO initially but not during reload. From-SVN: r21305
This commit is contained in:
Ken Raeburn
Ken Raeburn
parent
0d3ba7398c
commit
e4f5c5d630
@ -1,3 +1,24 @@
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Mon Jul 20 22:51:57 1998 Ken Raeburn <raeburn@cygnus.com>
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* mips.md (reload_outsi): Added missing REGNO call.
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(smulsi3_highpart, umulsi3_highpart): Provide prototype for
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function pointer.
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(mul_acc_di, mul_acc_64bit_di): Don't use match_op_dup, use
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another match_operator and compare the codes.
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* mips.h (MASK_DEBUG_E, MASK_DEBUG_I): Set to zero.
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* MIPS multiply pattern fixes:
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* mips.h (enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS):
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Add union classes for HI, LO, or HILO plus general registers.
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(GENERATE_MADD): Deleted.
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* mips.md (mulsi3_mult3): Don't disparage output-LO alternative.
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Add TARGET_MAD to condition.
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(mulsi3): Test HAVE_mulsi3_mult3, not specific flags.
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(mul_acc_si): Expand GENERATE_MADD here; it's the only use. Use
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"*d" for accumulator, to give preference to LO initially but not
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during reload.
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Mon Jul 20 16:16:38 1998 Dave Brolley <brolley@cygnus.com>
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* configure.in (enable_c_mbchar): New configure option.
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@ -342,11 +342,11 @@ extern void mips_select_section ();
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#define MASK_DEBUG_B 0x10000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
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#define MASK_DEBUG_C 0x08000000 /* don't expand seq, etc. */
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#define MASK_DEBUG_D 0x04000000 /* don't do define_split's */
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#define MASK_DEBUG_E 0x02000000 /* function_arg debug */
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#define MASK_DEBUG_E 0 /* function_arg debug */
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#define MASK_DEBUG_F 0
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#define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
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#define MASK_DEBUG_H 0 /* allow ints in FP registers */
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#define MASK_DEBUG_I 0x00200000 /* unused */
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#define MASK_DEBUG_I 0 /* unused */
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/* r4000 64 bit sizes */
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#define TARGET_INT64 (target_flags & MASK_INT64)
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@ -570,12 +570,10 @@ extern void mips_select_section ();
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#define SUBTARGET_TARGET_OPTIONS
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#define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2)))
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/* Generate three-operand multiply instructions for both SImode and DImode. */
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#define GENERATE_MULT3 (TARGET_MIPS3900 \
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&& !TARGET_MIPS16)
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#define GENERATE_MADD (TARGET_MIPS3900 \
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&& !TARGET_MIPS16)
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/* Macros to decide whether certain features are available or not,
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depending on the instruction set architecture level. */
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@ -1712,6 +1710,9 @@ enum reg_class
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LO_REG, /* lo register */
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HILO_REG, /* hilo register pair for 64 bit mode mult */
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MD_REGS, /* multiply/divide registers (hi/lo) */
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HI_AND_GR_REGS, /* union classes */
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LO_AND_GR_REGS,
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HILO_AND_GR_REGS,
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ST_REGS, /* status registers (fp status) */
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ALL_REGS, /* all registers */
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LIM_REG_CLASSES /* max value + 1 */
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@ -1738,6 +1739,9 @@ enum reg_class
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"LO_REG", \
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"HILO_REG", \
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"MD_REGS", \
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"HI_AND_GR_REGS", \
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"LO_AND_GR_REGS", \
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"HILO_AND_GR_REGS", \
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"ST_REGS", \
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"ALL_REGS" \
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}
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@ -1766,6 +1770,9 @@ enum reg_class
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{ 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
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{ 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
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{ 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
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{ 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
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{ 0xffffffff, 0x00000000, 0x00000002 }, \
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{ 0xffffffff, 0x00000000, 0x00000004 }, \
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{ 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
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{ 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
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}
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@ -1645,7 +1645,7 @@
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""
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"
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{
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if (GENERATE_MULT3)
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if (HAVE_mulsi3_mult3)
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emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
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else if (mips_cpu != PROCESSOR_R4000 || TARGET_MIPS16)
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emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
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@ -1655,13 +1655,14 @@
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}")
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(define_insn "mulsi3_mult3"
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[(set (match_operand:SI 0 "register_operand" "=d,?l")
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[(set (match_operand:SI 0 "register_operand" "=d,l")
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(mult:SI (match_operand:SI 1 "register_operand" "d,d")
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(match_operand:SI 2 "register_operand" "d,d")))
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(clobber (match_scratch:SI 3 "=h,h"))
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(clobber (match_scratch:SI 4 "=l,X"))
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(clobber (match_scratch:SI 5 "=a,a"))]
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"GENERATE_MULT3"
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"GENERATE_MULT3
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|| TARGET_MAD"
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"*
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{
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if (which_alternative == 1)
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@ -1709,22 +1710,29 @@
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(set_attr "mode" "SI")
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(set_attr "length" "3")]) ;; mult + mflo + delay
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;; Multiply-accumulate patterns
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;; For processors that can copy the output to a general register:
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;;
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;; The all-d alternative is needed because the combiner will find this
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;; pattern and then register alloc/reload will move registers around to
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;; make them fit, and we don't want to trigger unnecessary loads to LO.
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;; For the moment, that seems to mostly disable the "macc" instruction
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;; though; some "?" marks may be needed. Using "*d" helps, but causes
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;; stack spills in some cases.
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;;
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;; The last alternative should be made slightly less desirable, but adding
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;; "?" to the constraint is too strong, and causes values to be loaded into
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;; LO even when that's more costly. For now, using "*d" mostly does the
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;; trick.
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(define_insn "*mul_acc_si"
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[(set (match_operand:SI 0 "register_operand" "=l,d,d")
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[(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
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(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
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(match_operand:SI 2 "register_operand" "d,d,d"))
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(match_operand:SI 3 "register_operand" "0,l,d")))
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(match_operand:SI 3 "register_operand" "0,l,*d")))
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(clobber (match_scratch:SI 4 "=h,h,h"))
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(clobber (match_scratch:SI 5 "=X,3,l"))
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(clobber (match_scratch:SI 6 "=a,a,a"))
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(clobber (match_scratch:SI 7 "=X,X,d"))]
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"GENERATE_MADD"
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"TARGET_MIPS3900
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&& !TARGET_MIPS16"
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"*
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{
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static char *const madd[] = { \"madd\\t%1,%2\", \"madd\\t%0,%1,%2\" };
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@ -1736,6 +1744,7 @@
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(set_attr "mode" "SI")
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(set_attr "length" "1,1,2")])
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;; Split the above insn if we failed to get LO allocated.
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
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@ -1922,7 +1931,12 @@
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{
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rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx);
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rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx);
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rtx (*genfn)() = gen_xmulsi3_highpart_internal;
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#ifndef NO_MD_PROTOTYPES
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rtx (*genfn) PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
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#else
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rtx (*genfn) ();
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#endif
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genfn = gen_xmulsi3_highpart_internal;
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emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
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dummy, dummy2));
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DONE;
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@ -1939,7 +1953,12 @@
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{
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rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx);
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rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx);
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rtx (*genfn)() = gen_xmulsi3_highpart_internal;
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#ifndef NO_MD_PROTOTYPES
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rtx (*genfn) PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
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#else
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rtx (*genfn) ();
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#endif
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genfn = gen_xmulsi3_highpart_internal;
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emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
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dummy, dummy2));
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DONE;
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@ -2016,11 +2035,13 @@
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[(set (match_operand:DI 0 "register_operand" "+x")
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(plus:DI (mult:DI (match_operator:DI 3 "extend_operator"
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[(match_operand:SI 1 "register_operand" "d")])
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(match_op_dup:DI 3
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(match_operator:DI 4 "extend_operator"
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[(match_operand:SI 2 "register_operand" "d")]))
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(match_dup 0)))
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(clobber (match_scratch:SI 4 "=a"))]
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"TARGET_MAD && ! TARGET_64BIT"
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(clobber (match_scratch:SI 5 "=a"))]
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"TARGET_MAD
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&& ! TARGET_64BIT
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&& GET_CODE (operands[3]) == GET_CODE (operands[4])"
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"*
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{
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if (GET_CODE (operands[3]) == SIGN_EXTEND)
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@ -2036,12 +2057,14 @@
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[(set (match_operand:DI 0 "register_operand" "+a")
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(plus:DI (mult:DI (match_operator:DI 3 "extend_operator"
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[(match_operand:SI 1 "register_operand" "d")])
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(match_op_dup:DI 3
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(match_operator:DI 4 "extend_operator"
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[(match_operand:SI 2 "register_operand" "d")]))
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(match_dup 0)))
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(clobber (match_scratch:DI 4 "=l"))
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(clobber (match_scratch:DI 5 "=h"))]
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"TARGET_MAD && TARGET_64BIT"
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(clobber (match_scratch:SI 5 "=h"))
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(clobber (match_scratch:SI 6 "=l"))]
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"TARGET_MAD
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&& TARGET_64BIT
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&& GET_CODE (operands[3]) == GET_CODE (operands[4])"
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"*
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{
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if (GET_CODE (operands[3]) == SIGN_EXTEND)
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@ -5107,7 +5130,7 @@ move\\t%0,%z4\\n\\
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DONE;
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}
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/* FIXME: I don't know how to get a value into the HI register. */
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if (GET_CODE (operands[0]) == REG && GP_REG_P (operands[0]))
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if (GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])))
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{
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emit_move_insn (operands[0], operands[1]);
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DONE;
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