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rs6000: Rename DFP iterator and attr to DDTD and q
This is more in line with the other iterators we have, and a bit easier to read and write. * config/rs6000/dfp.md (D64_D128): Rename to ... (DDTD): ... this, throughout. (dfp_suffix): Rename to ... (q): ... this, throughout. From-SVN: r274218
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@ -1,3 +1,10 @@
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2019-08-08 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/dfp.md (D64_D128): Rename to ...
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(DDTD): ... this, throughout.
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(dfp_suffix): Rename to ...
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(q): ... this, throughout.
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2019-08-08 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/dfp.md (D64_D128): Move earlier in the file.
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@ -29,10 +29,9 @@
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])
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; Either of the two decimal modes.
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(define_mode_iterator D64_D128 [DD TD])
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(define_mode_iterator DDTD [DD TD])
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(define_mode_attr dfp_suffix [(DD "")
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(TD "q")])
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(define_mode_attr q [(DD "") (TD "q")])
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(define_insn "movsd_store"
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@ -157,43 +156,43 @@
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(set_attr "length" "8")])
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(define_insn "add<mode>3"
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[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
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(plus:D64_D128 (match_operand:D64_D128 1 "gpc_reg_operand" "%d")
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(match_operand:D64_D128 2 "gpc_reg_operand" "d")))]
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[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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(plus:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "%d")
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(match_operand:DDTD 2 "gpc_reg_operand" "d")))]
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"TARGET_DFP"
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"dadd<dfp_suffix> %0,%1,%2"
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"dadd<q> %0,%1,%2"
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[(set_attr "type" "dfp")])
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(define_insn "sub<mode>3"
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[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
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(minus:D64_D128 (match_operand:D64_D128 1 "gpc_reg_operand" "d")
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(match_operand:D64_D128 2 "gpc_reg_operand" "d")))]
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[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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(minus:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")
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(match_operand:DDTD 2 "gpc_reg_operand" "d")))]
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"TARGET_DFP"
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"dsub<dfp_suffix> %0,%1,%2"
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"dsub<q> %0,%1,%2"
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[(set_attr "type" "dfp")])
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(define_insn "mul<mode>3"
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[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
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(mult:D64_D128 (match_operand:D64_D128 1 "gpc_reg_operand" "%d")
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(match_operand:D64_D128 2 "gpc_reg_operand" "d")))]
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[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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(mult:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "%d")
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(match_operand:DDTD 2 "gpc_reg_operand" "d")))]
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"TARGET_DFP"
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"dmul<dfp_suffix> %0,%1,%2"
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"dmul<q> %0,%1,%2"
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[(set_attr "type" "dfp")])
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(define_insn "div<mode>3"
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[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
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(div:D64_D128 (match_operand:D64_D128 1 "gpc_reg_operand" "d")
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(match_operand:D64_D128 2 "gpc_reg_operand" "d")))]
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[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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(div:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")
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(match_operand:DDTD 2 "gpc_reg_operand" "d")))]
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"TARGET_DFP"
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"ddiv<dfp_suffix> %0,%1,%2"
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"ddiv<q> %0,%1,%2"
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[(set_attr "type" "dfp")])
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(define_insn "*cmp<mode>_internal1"
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[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
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(compare:CCFP (match_operand:D64_D128 1 "gpc_reg_operand" "d")
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(match_operand:D64_D128 2 "gpc_reg_operand" "d")))]
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(compare:CCFP (match_operand:DDTD 1 "gpc_reg_operand" "d")
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(match_operand:DDTD 2 "gpc_reg_operand" "d")))]
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"TARGET_DFP"
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"dcmpu<dfp_suffix> %0,%1,%2"
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"dcmpu<q> %0,%1,%2"
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[(set_attr "type" "dfp")])
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(define_insn "floatdidd2"
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@ -214,10 +213,10 @@
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;; This is the first stage of converting it to an integer type.
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(define_insn "ftrunc<mode>2"
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[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
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(fix:D64_D128 (match_operand:D64_D128 1 "gpc_reg_operand" "d")))]
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[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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(fix:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")))]
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"TARGET_DFP"
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"drintn<dfp_suffix>. 0,%0,%1,1"
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"drintn<q>. 0,%0,%1,1"
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[(set_attr "type" "dfp")])
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;; Convert a decimal64/128 whose value is an integer to an actual integer.
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@ -225,9 +224,9 @@
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(define_insn "fix<mode>di2"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
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(fix:DI (match_operand:D64_D128 1 "gpc_reg_operand" "d")))]
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(fix:DI (match_operand:DDTD 1 "gpc_reg_operand" "d")))]
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"TARGET_DFP"
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"dctfix<dfp_suffix> %0,%1"
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"dctfix<q> %0,%1"
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[(set_attr "type" "dfp")])
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;; Decimal builtin support
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@ -244,64 +243,61 @@
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(define_code_iterator DFP_TEST [eq lt gt unordered])
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(define_insn "dfp_ddedpd_<mode>"
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[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
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(unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i")
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(match_operand:D64_D128 2 "gpc_reg_operand" "d")]
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UNSPEC_DDEDPD))]
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[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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(unspec:DDTD [(match_operand:QI 1 "const_0_to_3_operand" "i")
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(match_operand:DDTD 2 "gpc_reg_operand" "d")]
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UNSPEC_DDEDPD))]
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"TARGET_DFP"
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"ddedpd<dfp_suffix> %1,%0,%2"
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"ddedpd<q> %1,%0,%2"
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[(set_attr "type" "dfp")])
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(define_insn "dfp_denbcd_<mode>"
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[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
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(unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i")
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(match_operand:D64_D128 2 "gpc_reg_operand" "d")]
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UNSPEC_DENBCD))]
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[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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(unspec:DDTD [(match_operand:QI 1 "const_0_to_1_operand" "i")
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(match_operand:DDTD 2 "gpc_reg_operand" "d")]
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UNSPEC_DENBCD))]
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"TARGET_DFP"
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"denbcd<dfp_suffix> %1,%0,%2"
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"denbcd<q> %1,%0,%2"
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[(set_attr "type" "dfp")])
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(define_insn "dfp_dxex_<mode>"
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[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
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(unspec:DI [(match_operand:D64_D128 1 "gpc_reg_operand" "d")]
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(unspec:DI [(match_operand:DDTD 1 "gpc_reg_operand" "d")]
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UNSPEC_DXEX))]
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"TARGET_DFP"
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"dxex<dfp_suffix> %0,%1"
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"dxex<q> %0,%1"
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[(set_attr "type" "dfp")])
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(define_insn "dfp_diex_<mode>"
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[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
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(unspec:D64_D128 [(match_operand:DI 1 "gpc_reg_operand" "d")
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(match_operand:D64_D128 2 "gpc_reg_operand" "d")]
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UNSPEC_DXEX))]
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[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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(unspec:DDTD [(match_operand:DI 1 "gpc_reg_operand" "d")
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(match_operand:DDTD 2 "gpc_reg_operand" "d")]
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UNSPEC_DXEX))]
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"TARGET_DFP"
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"diex<dfp_suffix> %0,%1,%2"
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"diex<q> %0,%1,%2"
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[(set_attr "type" "dfp")])
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(define_expand "dfptstsfi_<code>_<mode>"
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[(set (match_dup 3)
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(compare:CCFP
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(unspec:D64_D128
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[(match_operand:SI 1 "const_int_operand")
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(match_operand:D64_D128 2 "gpc_reg_operand")]
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UNSPEC_DTSTSFI)
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(match_dup 4)))
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(compare:CCFP (unspec:DDTD [(match_operand:SI 1 "const_int_operand")
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(match_operand:DDTD 2 "gpc_reg_operand")]
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UNSPEC_DTSTSFI)
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(const_int 0)))
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(set (match_operand:SI 0 "register_operand")
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(DFP_TEST:SI (match_dup 3)
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(DFP_TEST:SI (match_dup 3)
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(const_int 0)))
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]
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"TARGET_P9_MISC"
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{
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operands[3] = gen_reg_rtx (CCFPmode);
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operands[4] = const0_rtx;
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})
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(define_insn "*dfp_sgnfcnc_<mode>"
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[(set (match_operand:CCFP 0 "" "=y")
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(compare:CCFP
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(unspec:D64_D128 [(match_operand:SI 1 "const_int_operand" "n")
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(match_operand:D64_D128 2 "gpc_reg_operand" "d")]
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UNSPEC_DTSTSFI)
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(compare:CCFP
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(unspec:DDTD [(match_operand:SI 1 "const_int_operand" "n")
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(match_operand:DDTD 2 "gpc_reg_operand" "d")]
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UNSPEC_DTSTSFI)
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(match_operand:SI 3 "zero_constant" "j")))]
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"TARGET_P9_MISC"
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{
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@ -310,24 +306,24 @@
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immediate operand values greater than 63. */
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if (!(IN_RANGE (INTVAL (operands[1]), 0, 63)))
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operands[1] = GEN_INT (63);
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return "dtstsfi<dfp_suffix> %0,%1,%2";
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return "dtstsfi<q> %0,%1,%2";
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}
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[(set_attr "type" "fp")])
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(define_insn "dfp_dscli_<mode>"
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[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
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(unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
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(match_operand:QI 2 "immediate_operand" "i")]
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UNSPEC_DSCLI))]
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[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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(unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
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(match_operand:QI 2 "immediate_operand" "i")]
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UNSPEC_DSCLI))]
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"TARGET_DFP"
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"dscli<dfp_suffix> %0,%1,%2"
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"dscli<q> %0,%1,%2"
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[(set_attr "type" "dfp")])
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(define_insn "dfp_dscri_<mode>"
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[(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
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(unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
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(match_operand:QI 2 "immediate_operand" "i")]
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UNSPEC_DSCRI))]
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[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
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(unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
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(match_operand:QI 2 "immediate_operand" "i")]
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UNSPEC_DSCRI))]
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"TARGET_DFP"
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"dscri<dfp_suffix> %0,%1,%2"
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"dscri<q> %0,%1,%2"
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[(set_attr "type" "dfp")])
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