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re PR rtl-optimization/11327 (Non-optimal code when using MMX/SSE builtins)
PR target/11327
* config/i386/i386.c (BUILTIN_DESC_SWAP_OPERANDS): New.
(bdesc_2arg): Use it.
(ix86_expand_binop_builtin): Force operands into registers
when optimizing.
(ix86_expand_unop_builtin, ix86_expand_unop1_builtin,
ix86_expand_sse_compare, ix86_expand_sse_comi,
ix86_expand_builtin): Likewise.
From-SVN: r92988
This commit is contained in:
Richard Henderson
Richard Henderson
parent
051d824588
commit
e358acde2c
@ -1,3 +1,14 @@
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2005-01-05 Richard Henderson <rth@redhat.com>
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PR target/11327
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* config/i386/i386.c (BUILTIN_DESC_SWAP_OPERANDS): New.
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(bdesc_2arg): Use it.
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(ix86_expand_binop_builtin): Force operands into registers
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when optimizing.
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(ix86_expand_unop_builtin, ix86_expand_unop1_builtin,
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ix86_expand_sse_compare, ix86_expand_sse_comi,
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ix86_expand_builtin): Likewise.
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2005-01-05 Richard Henderson <rth@redhat.com>
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* config/ia64/ia64.c (rtx_needs_barrier): Handle CONST_VECTOR
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@ -12077,6 +12077,12 @@ do { \
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NULL, NULL_TREE); \
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} while (0)
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/* Bits for builtin_description.flag. */
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/* Set when we don't support the comparison natively, and should
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swap_comparison in order to support it. */
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#define BUILTIN_DESC_SWAP_OPERANDS 1
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struct builtin_description
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{
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const unsigned int mask;
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@ -12130,14 +12136,18 @@ static const struct builtin_description bdesc_2arg[] =
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{ MASK_SSE, CODE_FOR_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 },
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{ MASK_SSE, CODE_FOR_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 },
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{ MASK_SSE, CODE_FOR_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 },
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{ MASK_SSE, CODE_FOR_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, 1 },
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{ MASK_SSE, CODE_FOR_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, 1 },
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{ MASK_SSE, CODE_FOR_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT,
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BUILTIN_DESC_SWAP_OPERANDS },
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{ MASK_SSE, CODE_FOR_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE,
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BUILTIN_DESC_SWAP_OPERANDS },
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{ MASK_SSE, CODE_FOR_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 },
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{ MASK_SSE, CODE_FOR_maskncmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, EQ, 0 },
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{ MASK_SSE, CODE_FOR_maskncmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, LT, 0 },
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{ MASK_SSE, CODE_FOR_maskncmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, LE, 0 },
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{ MASK_SSE, CODE_FOR_maskncmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, LT, 1 },
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{ MASK_SSE, CODE_FOR_maskncmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, LE, 1 },
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{ MASK_SSE, CODE_FOR_maskncmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, LT,
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BUILTIN_DESC_SWAP_OPERANDS },
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{ MASK_SSE, CODE_FOR_maskncmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, LE,
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BUILTIN_DESC_SWAP_OPERANDS },
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{ MASK_SSE, CODE_FOR_maskncmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, UNORDERED, 0 },
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{ MASK_SSE, CODE_FOR_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 },
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{ MASK_SSE, CODE_FOR_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 },
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@ -12258,14 +12268,18 @@ static const struct builtin_description bdesc_2arg[] =
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{ MASK_SSE2, CODE_FOR_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 },
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{ MASK_SSE2, CODE_FOR_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 },
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{ MASK_SSE2, CODE_FOR_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 },
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{ MASK_SSE2, CODE_FOR_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, 1 },
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{ MASK_SSE2, CODE_FOR_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, 1 },
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{ MASK_SSE2, CODE_FOR_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT,
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BUILTIN_DESC_SWAP_OPERANDS },
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{ MASK_SSE2, CODE_FOR_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE,
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BUILTIN_DESC_SWAP_OPERANDS },
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{ MASK_SSE2, CODE_FOR_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 },
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{ MASK_SSE2, CODE_FOR_maskncmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, EQ, 0 },
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{ MASK_SSE2, CODE_FOR_maskncmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, LT, 0 },
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{ MASK_SSE2, CODE_FOR_maskncmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, LE, 0 },
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{ MASK_SSE2, CODE_FOR_maskncmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, LT, 1 },
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{ MASK_SSE2, CODE_FOR_maskncmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, LE, 1 },
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{ MASK_SSE2, CODE_FOR_maskncmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, LT,
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BUILTIN_DESC_SWAP_OPERANDS },
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{ MASK_SSE2, CODE_FOR_maskncmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, LE,
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BUILTIN_DESC_SWAP_OPERANDS },
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{ MASK_SSE2, CODE_FOR_maskncmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, UNORDERED, 0 },
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{ MASK_SSE2, CODE_FOR_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 },
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{ MASK_SSE2, CODE_FOR_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 },
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@ -13137,7 +13151,7 @@ ix86_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
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if (VECTOR_MODE_P (mode1))
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op1 = safe_vector_operand (op1, mode1);
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if (! target
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if (optimize || !target
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|| GET_MODE (target) != tmode
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|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
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target = gen_reg_rtx (tmode);
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@ -13155,9 +13169,11 @@ ix86_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
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|| (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode))
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abort ();
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if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
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if ((optimize && !register_operand (op0, mode0))
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|| !(*insn_data[icode].operand[1].predicate) (op0, mode0))
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op0 = copy_to_mode_reg (mode0, op0);
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if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
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if ((optimize && !register_operand (op1, mode1))
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|| !(*insn_data[icode].operand[2].predicate) (op1, mode1))
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op1 = copy_to_mode_reg (mode1, op1);
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/* In the commutative cases, both op0 and op1 are nonimmediate_operand,
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@ -13210,7 +13226,7 @@ ix86_expand_unop_builtin (enum insn_code icode, tree arglist,
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enum machine_mode tmode = insn_data[icode].operand[0].mode;
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enum machine_mode mode0 = insn_data[icode].operand[1].mode;
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if (! target
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if (optimize || !target
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|| GET_MODE (target) != tmode
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|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
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target = gen_reg_rtx (tmode);
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@ -13221,7 +13237,8 @@ ix86_expand_unop_builtin (enum insn_code icode, tree arglist,
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if (VECTOR_MODE_P (mode0))
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op0 = safe_vector_operand (op0, mode0);
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if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
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if ((optimize && !register_operand (op0, mode0))
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|| ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
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op0 = copy_to_mode_reg (mode0, op0);
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}
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@ -13244,7 +13261,7 @@ ix86_expand_unop1_builtin (enum insn_code icode, tree arglist, rtx target)
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enum machine_mode tmode = insn_data[icode].operand[0].mode;
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enum machine_mode mode0 = insn_data[icode].operand[1].mode;
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if (! target
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if (optimize || !target
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|| GET_MODE (target) != tmode
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|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
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target = gen_reg_rtx (tmode);
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@ -13252,7 +13269,8 @@ ix86_expand_unop1_builtin (enum insn_code icode, tree arglist, rtx target)
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if (VECTOR_MODE_P (mode0))
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op0 = safe_vector_operand (op0, mode0);
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if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
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if ((optimize && !register_operand (op0, mode0))
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|| ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
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op0 = copy_to_mode_reg (mode0, op0);
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op1 = op0;
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@ -13290,7 +13308,7 @@ ix86_expand_sse_compare (const struct builtin_description *d, tree arglist,
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/* Swap operands if we have a comparison that isn't available in
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hardware. */
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if (d->flag)
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if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
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{
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rtx tmp = gen_reg_rtx (mode1);
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emit_move_insn (tmp, op1);
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@ -13298,14 +13316,16 @@ ix86_expand_sse_compare (const struct builtin_description *d, tree arglist,
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op0 = tmp;
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}
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if (! target
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if (optimize || !target
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|| GET_MODE (target) != tmode
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|| ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
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target = gen_reg_rtx (tmode);
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if (! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
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if ((optimize && !register_operand (op0, mode0))
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|| ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
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op0 = copy_to_mode_reg (mode0, op0);
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if (! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
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if ((optimize && !register_operand (op1, mode1))
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|| ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
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op1 = copy_to_mode_reg (mode1, op1);
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op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
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@ -13339,7 +13359,7 @@ ix86_expand_sse_comi (const struct builtin_description *d, tree arglist,
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/* Swap operands if we have a comparison that isn't available in
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hardware. */
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if (d->flag)
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if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
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{
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rtx tmp = op1;
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op1 = op0;
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@ -13350,9 +13370,11 @@ ix86_expand_sse_comi (const struct builtin_description *d, tree arglist,
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emit_move_insn (target, const0_rtx);
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target = gen_rtx_SUBREG (QImode, target, 0);
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if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
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if ((optimize && !register_operand (op0, mode0))
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|| !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
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op0 = copy_to_mode_reg (mode0, op0);
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if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
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if ((optimize && !register_operand (op1, mode1))
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|| !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
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op1 = copy_to_mode_reg (mode1, op1);
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op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
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@ -13449,7 +13471,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
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op0 = copy_to_mode_reg (mode0, op0);
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if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
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if ((optimize && !register_operand (op1, mode1))
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|| ! (*insn_data[icode].operand[2].predicate) (op1, mode1))
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op1 = copy_to_mode_reg (mode1, op1);
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if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
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{
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@ -13470,7 +13493,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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case IX86_BUILTIN_MASKMOVQ:
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case IX86_BUILTIN_MASKMOVDQU:
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icode = (fcode == IX86_BUILTIN_MASKMOVQ
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? (TARGET_64BIT ? CODE_FOR_mmx_maskmovq_rex : CODE_FOR_mmx_maskmovq)
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? (TARGET_64BIT ? CODE_FOR_mmx_maskmovq_rex
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: CODE_FOR_mmx_maskmovq)
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: (TARGET_64BIT ? CODE_FOR_sse2_maskmovdqu_rex64
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: CODE_FOR_sse2_maskmovdqu));
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/* Note the arg order is different from the operand order. */
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@ -13537,12 +13561,11 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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mode0 = insn_data[icode].operand[1].mode;
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mode1 = insn_data[icode].operand[2].mode;
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if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
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op0 = copy_to_mode_reg (mode0, op0);
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op0 = force_reg (mode0, op0);
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op1 = gen_rtx_MEM (mode1, copy_to_mode_reg (Pmode, op1));
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if (target == 0
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if (optimize || target == 0
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|| GET_MODE (target) != tmode
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|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
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|| !register_operand (target, tmode))
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target = gen_reg_rtx (tmode);
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pat = GEN_FCN (icode) (target, op0, op1);
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if (! pat)
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@ -13566,8 +13589,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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mode1 = insn_data[icode].operand[1].mode;
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op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
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if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
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op1 = copy_to_mode_reg (mode1, op1);
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op1 = force_reg (mode1, op1);
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pat = GEN_FCN (icode) (op0, op1);
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if (! pat)
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@ -13610,7 +13632,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
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op0 = copy_to_mode_reg (mode0, op0);
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if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
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if ((optimize && !register_operand (op1, mode1))
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|| !(*insn_data[icode].operand[2].predicate) (op1, mode1))
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op1 = copy_to_mode_reg (mode1, op1);
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if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
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{
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@ -13618,7 +13641,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
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error ("mask must be an immediate");
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return gen_reg_rtx (tmode);
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}
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if (target == 0
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if (optimize || target == 0
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|| GET_MODE (target) != tmode
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|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
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target = gen_reg_rtx (tmode);
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