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alpha.c (reg_or_6bit_operand): Recognize CONSTANT_P_RTX.
* alpha.c (reg_or_6bit_operand): Recognize CONSTANT_P_RTX. (reg_or_8bit_operand, cint8_operand, add_operand): Likewise. (sext_add_operand, and_operand, or_operand): Likewise. (reg_or_cint_operand, some_operand, input_operand): Likewise. * alpha.h (PREDICATE_CODES): Add CONSTANT_P_RTX where needed. From-SVN: r20847
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@ -337,6 +337,7 @@ reg_or_6bit_operand (op, mode)
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{
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return ((GET_CODE (op) == CONST_INT
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&& (unsigned HOST_WIDE_INT) INTVAL (op) < 64)
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|| GET_CODE (op) == CONSTANT_P_RTX
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|| register_operand (op, mode));
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}
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@ -350,6 +351,7 @@ reg_or_8bit_operand (op, mode)
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{
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return ((GET_CODE (op) == CONST_INT
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&& (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
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|| GET_CODE (op) == CONSTANT_P_RTX
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|| register_operand (op, mode));
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}
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@ -360,8 +362,9 @@ cint8_operand (op, mode)
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register rtx op;
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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return (GET_CODE (op) == CONST_INT
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&& (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100);
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return ((GET_CODE (op) == CONST_INT
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&& (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
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|| GET_CODE (op) == CONSTANT_P_RTX);
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}
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/* Return 1 if the operand is a valid second operand to an add insn. */
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@ -375,6 +378,8 @@ add_operand (op, mode)
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return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')
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|| CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')
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|| CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'));
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else if (GET_CODE (op) == CONSTANT_P_RTX)
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return 1;
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return register_operand (op, mode);
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}
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@ -390,6 +395,8 @@ sext_add_operand (op, mode)
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if (GET_CODE (op) == CONST_INT)
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return ((unsigned HOST_WIDE_INT) INTVAL (op) < 255
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|| (unsigned HOST_WIDE_INT) (- INTVAL (op)) < 255);
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else if (GET_CODE (op) == CONSTANT_P_RTX)
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return 1;
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return register_operand (op, mode);
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}
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@ -420,6 +427,8 @@ and_operand (op, mode)
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return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
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|| (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
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|| zap_mask (INTVAL (op)));
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else if (GET_CODE (op) == CONSTANT_P_RTX)
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return 1;
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return register_operand (op, mode);
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}
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@ -434,6 +443,8 @@ or_operand (op, mode)
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if (GET_CODE (op) == CONST_INT)
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return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
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|| (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100);
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else if (GET_CODE (op) == CONSTANT_P_RTX)
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return 1;
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return register_operand (op, mode);
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}
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@ -532,7 +543,9 @@ reg_or_cint_operand (op, mode)
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register rtx op;
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enum machine_mode mode;
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{
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return GET_CODE (op) == CONST_INT || register_operand (op, mode);
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return (GET_CODE (op) == CONST_INT
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|| GET_CODE (op) == CONSTANT_P_RTX
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|| register_operand (op, mode));
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}
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/* Return 1 if OP is something that can be reloaded into a register;
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@ -548,8 +561,8 @@ some_operand (op, mode)
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switch (GET_CODE (op))
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{
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case REG: case MEM: case CONST_DOUBLE:
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case CONST_INT: case LABEL_REF: case SYMBOL_REF: case CONST:
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case REG: case MEM: case CONST_DOUBLE: case CONST_INT: case LABEL_REF:
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case SYMBOL_REF: case CONST: case CONSTANT_P_RTX:
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return 1;
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case SUBREG:
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@ -580,7 +593,7 @@ input_operand (op, mode)
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case LABEL_REF:
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case SYMBOL_REF:
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case CONST:
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/* This handles both the Windows/NT and OSF cases. */
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/* This handles both the Windows/NT and OSF cases. */
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return mode == ptr_mode || mode == DImode;
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case REG:
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@ -598,6 +611,7 @@ input_operand (op, mode)
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return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
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case CONST_INT:
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case CONSTANT_P_RTX:
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return mode == QImode || mode == HImode || add_operand (op, mode);
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default:
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@ -2181,36 +2181,36 @@ do { \
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}
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/* Define the codes that are matched by predicates in alpha.c. */
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#define PREDICATE_CODES \
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{"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
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{"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
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{"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
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{"cint8_operand", {CONST_INT}}, \
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{"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
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{"add_operand", {SUBREG, REG, CONST_INT}}, \
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{"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
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{"const48_operand", {CONST_INT}}, \
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{"and_operand", {SUBREG, REG, CONST_INT}}, \
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{"or_operand", {SUBREG, REG, CONST_INT}}, \
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{"mode_mask_operand", {CONST_INT}}, \
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{"mul8_operand", {CONST_INT}}, \
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{"mode_width_operand", {CONST_INT}}, \
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{"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
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{"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
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{"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
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{"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
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{"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
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{"fp0_operand", {CONST_DOUBLE}}, \
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{"current_file_function_operand", {SYMBOL_REF}}, \
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{"call_operand", {REG, SYMBOL_REF}}, \
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{"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
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SYMBOL_REF, CONST, LABEL_REF}}, \
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{"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
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SYMBOL_REF, CONST, LABEL_REF}}, \
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{"aligned_memory_operand", {MEM}}, \
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{"unaligned_memory_operand", {MEM}}, \
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{"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
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{"any_memory_operand", {MEM}}, \
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#define PREDICATE_CODES \
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{"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
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{"reg_or_6bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
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{"reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
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{"cint8_operand", {CONST_INT, CONSTANT_P_RTX}}, \
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{"reg_or_cint_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
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{"add_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
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{"sext_add_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
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{"const48_operand", {CONST_INT}}, \
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{"and_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
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{"or_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \
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{"mode_mask_operand", {CONST_INT}}, \
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{"mul8_operand", {CONST_INT}}, \
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{"mode_width_operand", {CONST_INT}}, \
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{"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
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{"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
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{"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
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{"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
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{"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
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{"fp0_operand", {CONST_DOUBLE}}, \
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{"current_file_function_operand", {SYMBOL_REF}}, \
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{"call_operand", {REG, SYMBOL_REF}}, \
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{"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
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SYMBOL_REF, CONST, LABEL_REF, CONSTANT_P_RTX}}, \
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{"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
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SYMBOL_REF, CONST, LABEL_REF, CONSTANT_P_RTX}}, \
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{"aligned_memory_operand", {MEM}}, \
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{"unaligned_memory_operand", {MEM}}, \
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{"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
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{"any_memory_operand", {MEM}}, \
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{"hard_fp_register_operand", {SUBREG, REG}},
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/* Tell collect that the object format is ECOFF. */
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