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invoke.texi (ARC Options): Copy-edit to fix punctuation, markup, and similar issues.
2017-02-28 Sandra Loosemore <sandra@codesourcery.com> gcc/ * doc/invoke.texi (ARC Options): Copy-edit to fix punctuation, markup, and similar issues. Remove @opindex entries for things that aren't options. Add missing -mmpy-option entries. From-SVN: r245800
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Sandra Loosemore
Sandra Loosemore
parent
da1a9ced78
commit
e287080d1c
gcc
@ -1,3 +1,9 @@
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2017-02-28 Sandra Loosemore <sandra@codesourcery.com>
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* doc/invoke.texi (ARC Options): Copy-edit to fix punctuation,
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markup, and similar issues. Remove @opindex entries for things
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that aren't options. Add missing -mmpy-option entries.
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2017-02-28 Jakub Jelinek <jakub@redhat.com>
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PR tree-optimization/79737
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@ -14248,70 +14248,58 @@ Compile for ARC EM.
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Compile for ARC HS.
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@item em
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@opindex em
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Compile for ARC EM cpu with no hardware extension.
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Compile for ARC EM CPU with no hardware extensions.
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@item em4
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@opindex em4
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Compile for ARC EM4 cpu.
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Compile for ARC EM4 CPU.
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@item em4_dmips
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@opindex em4_dmips
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Compile for ARC EM4 DMIPS cpu.
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Compile for ARC EM4 DMIPS CPU.
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@item em4_fpus
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@opindex em4_fpus
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Compile for ARC EM4 DMIPS cpu with single precision floating point
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Compile for ARC EM4 DMIPS CPU with the single-precision floating-point
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extension.
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@item em4_fpuda
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@opindex em4_fpuda
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Compile for ARC EM4 DMIPS cpu with single precision floating point and
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double assists instructions.
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Compile for ARC EM4 DMIPS CPU with single-precision floating-point and
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double assist instructions.
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@item hs
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@opindex hs
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Compile for ARC HS cpu with no hardware extension, except the atomic
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Compile for ARC HS CPU with no hardware extensions except the atomic
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instructions.
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@item hs34
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@opindex hs34
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Compile for ARC HS34 cpu.
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Compile for ARC HS34 CPU.
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@item hs38
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@opindex hs38
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Compile for ARC HS38 cpu.
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Compile for ARC HS38 CPU.
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@item hs38_linux
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@opindex hs38_linux
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Compile for ARC HS38 cpu with all hardware extensions on.
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Compile for ARC HS38 CPU with all hardware extensions on.
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@item arc600_norm
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@opindex arc600_norm
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Compile for ARC 600 cpu with norm instruction enabled.
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Compile for ARC 600 CPU with @code{norm} instructions enabled.
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@item arc600_mul32x16
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@opindex arc600_mul32x16
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Compile for ARC 600 cpu with norm and mul32x16 instructions enabled.
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Compile for ARC 600 CPU with @code{norm} and 32x16-bit multiply
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instructions enabled.
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@item arc600_mul64
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@opindex arc600_mul64
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Compile for ARC 600 cpu with norm and mul64 instructions enabled.
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Compile for ARC 600 CPU with @code{norm} and @code{mul64}-family
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instructions enabled.
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@item arc601_norm
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@opindex arc601_norm
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Compile for ARC 601 cpu with norm instruction enabled.
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Compile for ARC 601 CPU with @code{norm} instructions enabled.
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@item arc601_mul32x16
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@opindex arc601_mul32x16
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Compile for ARC 601 cpu with norm and mul32x16 instructions enabled.
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Compile for ARC 601 CPU with @code{norm} and 32x16-bit multiply
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instructions enabled.
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@item arc601_mul64
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@opindex arc601_mul64
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Compile for ARC 601 cpu with norm and mul64 instructions enabled.
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Compile for ARC 601 CPU with @code{norm} and @code{mul64}-family
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instructions enabled.
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@item nps400
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@opindex nps400
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Compile for ARC 700 on NPS400 chip.
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@end table
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@ -14320,52 +14308,54 @@ Compile for ARC 700 on NPS400 chip.
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@opindex mdpfp
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@itemx -mdpfp-compact
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@opindex mdpfp-compact
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FPX: Generate Double Precision FPX instructions, tuned for the compact
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Generate double-precision FPX instructions, tuned for the compact
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implementation.
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@item -mdpfp-fast
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@opindex mdpfp-fast
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FPX: Generate Double Precision FPX instructions, tuned for the fast
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Generate double-precision FPX instructions, tuned for the fast
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implementation.
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@item -mno-dpfp-lrsr
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@opindex mno-dpfp-lrsr
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Disable LR and SR instructions from using FPX extension aux registers.
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Disable @code{lr} and @code{sr} instructions from using FPX extension
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aux registers.
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@item -mea
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@opindex mea
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Generate Extended arithmetic instructions. Currently only
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Generate extended arithmetic instructions. Currently only
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@code{divaw}, @code{adds}, @code{subs}, and @code{sat16} are
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supported. This is always enabled for @option{-mcpu=ARC700}.
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@item -mno-mpy
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@opindex mno-mpy
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Do not generate mpy instructions for ARC700. This instruction is
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Do not generate @code{mpy}-family instructions for ARC700. This option is
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deprecated.
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@item -mmul32x16
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@opindex mmul32x16
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Generate 32x16 bit multiply and mac instructions.
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Generate 32x16-bit multiply and multiply-accumulate instructions.
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@item -mmul64
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@opindex mmul64
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Generate mul64 and mulu64 instructions. Only valid for @option{-mcpu=ARC600}.
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Generate @code{mul64} and @code{mulu64} instructions.
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Only valid for @option{-mcpu=ARC600}.
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@item -mnorm
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@opindex mnorm
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Generate norm instruction. This is the default if @option{-mcpu=ARC700}
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Generate @code{norm} instructions. This is the default if @option{-mcpu=ARC700}
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is in effect.
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@item -mspfp
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@opindex mspfp
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@itemx -mspfp-compact
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@opindex mspfp-compact
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FPX: Generate Single Precision FPX instructions, tuned for the compact
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Generate single-precision FPX instructions, tuned for the compact
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implementation.
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@item -mspfp-fast
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@opindex mspfp-fast
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FPX: Generate Single Precision FPX instructions, tuned for the fast
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Generate single-precision FPX instructions, tuned for the fast
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implementation.
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@item -msimd
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@ -14376,28 +14366,29 @@ builtins. Only valid for @option{-mcpu=ARC700}.
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@item -msoft-float
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@opindex msoft-float
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This option ignored; it is provided for compatibility purposes only.
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Software floating point code is emitted by default, and this default
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can overridden by FPX options; @samp{mspfp}, @samp{mspfp-compact}, or
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@samp{mspfp-fast} for single precision, and @samp{mdpfp},
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@samp{mdpfp-compact}, or @samp{mdpfp-fast} for double precision.
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Software floating-point code is emitted by default, and this default
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can overridden by FPX options; @option{-mspfp}, @option{-mspfp-compact}, or
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@option{-mspfp-fast} for single precision, and @option{-mdpfp},
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@option{-mdpfp-compact}, or @option{-mdpfp-fast} for double precision.
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@item -mswap
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@opindex mswap
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Generate swap instructions.
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Generate @code{swap} instructions.
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@item -matomic
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@opindex matomic
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This enables Locked Load/Store Conditional extension to implement
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atomic memopry built-in functions. Not available for ARC 6xx or ARC
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This enables use of the locked load/store conditional extension to implement
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atomic memory built-in functions. Not available for ARC 6xx or ARC
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EM cores.
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@item -mdiv-rem
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@opindex mdiv-rem
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Enable DIV/REM instructions for ARCv2 cores.
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Enable @code{div} and @code{rem} instructions for ARCv2 cores.
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@item -mcode-density
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@opindex mcode-density
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Enable code density instructions for ARC EM, default on for ARC HS.
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Enable code density instructions for ARC EM.
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This option is on by default for ARC HS.
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@item -mll64
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@opindex mll64
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@ -14409,47 +14400,61 @@ Specify thread pointer register number.
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@item -mmpy-option=@var{multo}
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@opindex mmpy-option
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Compile ARCv2 code with a multiplier design option. @samp{wlh1} is
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the default value. The recognized values for @var{multo} are:
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Compile ARCv2 code with a multiplier design option. You can specify
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the option using either a string or numeric value for @var{multo}.
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@samp{wlh1} is the default value. The recognized values are:
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@table @samp
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@item 0
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@itemx none
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No multiplier available.
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@item 1
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@opindex w
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The multiply option is set to w: 16x16 multiplier, fully pipelined.
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The following instructions are enabled: MPYW, and MPYUW.
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@itemx w
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16x16 multiplier, fully pipelined.
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The following instructions are enabled: @code{mpyw} and @code{mpyuw}.
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@item 2
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@opindex wlh1
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The multiply option is set to wlh1: 32x32 multiplier, fully
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@itemx wlh1
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32x32 multiplier, fully
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pipelined (1 stage). The following instructions are additionally
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enabled: MPY, MPYU, MPYM, MPYMU, and MPY_S.
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enabled: @code{mpy}, @code{mpyu}, @code{mpym}, @code{mpymu}, and @code{mpy_s}.
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@item 3
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@opindex wlh2
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The multiply option is set to wlh2: 32x32 multiplier, fully pipelined
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(2 stages). The following instructions are additionally enabled: MPY,
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MPYU, MPYM, MPYMU, and MPY_S.
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@itemx wlh2
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32x32 multiplier, fully pipelined
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(2 stages). The following instructions are additionally enabled: @code{mpy},
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@code{mpyu}, @code{mpym}, @code{mpymu}, and @code{mpy_s}.
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@item 4
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@opindex wlh3
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The multiply option is set to wlh3: Two 16x16 multiplier, blocking,
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sequential. The following instructions are additionally enabled: MPY,
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MPYU, MPYM, MPYMU, and MPY_S.
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@itemx wlh3
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Two 16x16 multipliers, blocking,
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sequential. The following instructions are additionally enabled: @code{mpy},
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@code{mpyu}, @code{mpym}, @code{mpymu}, and @code{mpy_s}.
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@item 5
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@opindex wlh4
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The multiply option is set to wlh4: One 16x16 multiplier, blocking,
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sequential. The following instructions are additionally enabled: MPY,
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MPYU, MPYM, MPYMU, and MPY_S.
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@itemx wlh4
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One 16x16 multiplier, blocking,
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sequential. The following instructions are additionally enabled: @code{mpy},
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@code{mpyu}, @code{mpym}, @code{mpymu}, and @code{mpy_s}.
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@item 6
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@opindex wlh5
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The multiply option is set to wlh5: One 32x4 multiplier, blocking,
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sequential. The following instructions are additionally enabled: MPY,
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MPYU, MPYM, MPYMU, and MPY_S.
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@itemx wlh5
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One 32x4 multiplier, blocking,
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sequential. The following instructions are additionally enabled: @code{mpy},
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@code{mpyu}, @code{mpym}, @code{mpymu}, and @code{mpy_s}.
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@item 7
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@itemx plus_dmpy
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ARC HS SIMD support.
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@item 8
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@itemx plus_macd
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ARC HS SIMD support.
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@item 9
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@itemx plus_qmacw
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ARC HS SIMD support.
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@end table
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@ -14457,82 +14462,70 @@ This option is only available for ARCv2 cores@.
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@item -mfpu=@var{fpu}
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@opindex mfpu
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Enables specific floating-point hardware extension for ARCv2
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core. Supported values for @var{fpu} are:
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Enables support for specific floating-point hardware extensions for ARCv2
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cores. Supported values for @var{fpu} are:
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@table @samp
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@item fpus
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@opindex fpus
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Enables support for single precision floating point hardware
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Enables support for single-precision floating-point hardware
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extensions@.
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@item fpud
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@opindex fpud
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Enables support for double precision floating point hardware
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extensions. The single precision floating point extension is also
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Enables support for double-precision floating-point hardware
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extensions. The single-precision floating-point extension is also
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enabled. Not available for ARC EM@.
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@item fpuda
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@opindex fpuda
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Enables support for double precision floating point hardware
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extensions using double precision assist instructions. The single
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precision floating point extension is also enabled. This option is
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Enables support for double-precision floating-point hardware
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extensions using double-precision assist instructions. The single-precision
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floating-point extension is also enabled. This option is
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only available for ARC EM@.
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@item fpuda_div
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@opindex fpuda_div
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Enables support for double precision floating point hardware
|
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extensions using double precision assist instructions, and simple
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precision square-root and divide hardware extensions. The single
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precision floating point extension is also enabled. This option is
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Enables support for double-precision floating-point hardware
|
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extensions using double-precision assist instructions.
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The single-precision floating-point, square-root, and divide
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extensions are also enabled. This option is
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only available for ARC EM@.
|
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|
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@item fpuda_fma
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@opindex fpuda_fma
|
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Enables support for double precision floating point hardware
|
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extensions using double precision assist instructions, and simple
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precision fused multiple and add hardware extension. The single
|
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precision floating point extension is also enabled. This option is
|
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Enables support for double-precision floating-point hardware
|
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extensions using double-precision assist instructions.
|
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The single-precision floating-point and fused multiply and add
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hardware extensions are also enabled. This option is
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only available for ARC EM@.
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@item fpuda_all
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@opindex fpuda_all
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Enables support for double precision floating point hardware
|
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extensions using double precision assist instructions, and all simple
|
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precision hardware extensions. The single precision floating point
|
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extension is also enabled. This option is only available for ARC EM@.
|
||||
Enables support for double-precision floating-point hardware
|
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extensions using double-precision assist instructions.
|
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All single-precision floating-point hardware extensions are also
|
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enabled. This option is only available for ARC EM@.
|
||||
|
||||
@item fpus_div
|
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@opindex fpus_div
|
||||
Enables support for single precision floating point, and single
|
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precision square-root and divide hardware extensions@.
|
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Enables support for single-precision floating-point, square-root and divide
|
||||
hardware extensions@.
|
||||
|
||||
@item fpud_div
|
||||
@opindex fpud_div
|
||||
Enables support for double precision floating point, and double
|
||||
precision square-root and divide hardware extensions. This option
|
||||
Enables support for double-precision floating-point, square-root and divide
|
||||
hardware extensions. This option
|
||||
includes option @samp{fpus_div}. Not available for ARC EM@.
|
||||
|
||||
@item fpus_fma
|
||||
@opindex fpus_fma
|
||||
Enables support for single precision floating point, and single
|
||||
precision fused multiple and add hardware extensions@.
|
||||
Enables support for single-precision floating-point and
|
||||
fused multiply and add hardware extensions@.
|
||||
|
||||
@item fpud_fma
|
||||
@opindex fpud_fma
|
||||
Enables support for double precision floating point, and double
|
||||
precision fused multiple and add hardware extensions. This option
|
||||
Enables support for double-precision floating-point and
|
||||
fused multiply and add hardware extensions. This option
|
||||
includes option @samp{fpus_fma}. Not available for ARC EM@.
|
||||
|
||||
@item fpus_all
|
||||
@opindex fpus_all
|
||||
Enables support for all single precision floating point hardware
|
||||
Enables support for all single-precision floating-point hardware
|
||||
extensions@.
|
||||
|
||||
@item fpud_all
|
||||
@opindex fpud_all
|
||||
Enables support for all single and double precision floating point
|
||||
Enables support for all single- and double-precision floating-point
|
||||
hardware extensions. Not available for ARC EM@.
|
||||
|
||||
@end table
|
||||
@ -14553,15 +14546,15 @@ deprecated.
|
||||
|
||||
@item -mdvbf
|
||||
@opindex mdvbf
|
||||
Passed down to the assembler to enable the dual viterbi butterfly
|
||||
Passed down to the assembler to enable the dual Viterbi butterfly
|
||||
extension. Also sets the preprocessor symbol @code{__Xdvbf}. This
|
||||
option is deprecated.
|
||||
|
||||
@c ARC700 4.10 extension instruction
|
||||
@item -mlock
|
||||
@opindex mlock
|
||||
Passed down to the assembler to enable the Locked Load/Store
|
||||
Conditional extension. Also sets the preprocessor symbol
|
||||
Passed down to the assembler to enable the locked load/store
|
||||
conditional extension. Also sets the preprocessor symbol
|
||||
@code{__Xlock}.
|
||||
|
||||
@item -mmac-d16
|
||||
@ -14577,7 +14570,7 @@ Passed down to the assembler. Also sets the preprocessor symbol
|
||||
@c ARC700 4.10 extension instruction
|
||||
@item -mrtsc
|
||||
@opindex mrtsc
|
||||
Passed down to the assembler to enable the 64-bit Time-Stamp Counter
|
||||
Passed down to the assembler to enable the 64-bit time-stamp counter
|
||||
extension instruction. Also sets the preprocessor symbol
|
||||
@code{__Xrtsc}. This option is deprecated.
|
||||
|
||||
@ -14590,13 +14583,13 @@ extension instruction. Also sets the preprocessor symbol
|
||||
|
||||
@item -mtelephony
|
||||
@opindex mtelephony
|
||||
Passed down to the assembler to enable dual and single operand
|
||||
Passed down to the assembler to enable dual- and single-operand
|
||||
instructions for telephony. Also sets the preprocessor symbol
|
||||
@code{__Xtelephony}. This option is deprecated.
|
||||
|
||||
@item -mxy
|
||||
@opindex mxy
|
||||
Passed down to the assembler to enable the XY Memory extension. Also
|
||||
Passed down to the assembler to enable the XY memory extension. Also
|
||||
sets the preprocessor symbol @code{__Xxy}.
|
||||
|
||||
@end table
|
||||
@ -14642,12 +14635,12 @@ The following options control the semantics of generated code:
|
||||
@table @gcctabopt
|
||||
@item -mlong-calls
|
||||
@opindex mlong-calls
|
||||
Generate call insns as register indirect calls, thus providing access
|
||||
Generate calls as register indirect calls, thus providing access
|
||||
to the full 32-bit address range.
|
||||
|
||||
@item -mmedium-calls
|
||||
@opindex mmedium-calls
|
||||
Don't use less than 25 bit addressing range for calls, which is the
|
||||
Don't use less than 25-bit addressing range for calls, which is the
|
||||
offset available for an unconditional branch-and-link
|
||||
instruction. Conditional execution of function calls is suppressed, to
|
||||
allow use of the 25-bit range, rather than the 21-bit range with
|
||||
@ -14689,27 +14682,30 @@ Enable bbit peephole2.
|
||||
@item -mno-brcc
|
||||
@opindex mno-brcc
|
||||
This option disables a target-specific pass in @file{arc_reorg} to
|
||||
generate @code{BRcc} instructions. It has no effect on @code{BRcc}
|
||||
generation driven by the combiner pass.
|
||||
generate compare-and-branch (@code{br@var{cc}}) instructions.
|
||||
It has no effect on
|
||||
generation of these instructions driven by the combiner pass.
|
||||
|
||||
@item -mcase-vector-pcrel
|
||||
@opindex mcase-vector-pcrel
|
||||
Use pc-relative switch case tables - this enables case table shortening.
|
||||
Use PC-relative switch case tables to enable case table shortening.
|
||||
This is the default for @option{-Os}.
|
||||
|
||||
@item -mcompact-casesi
|
||||
@opindex mcompact-casesi
|
||||
Enable compact casesi pattern. This is the default for @option{-Os},
|
||||
Enable compact @code{casesi} pattern. This is the default for @option{-Os},
|
||||
and only available for ARCv1 cores.
|
||||
|
||||
@item -mno-cond-exec
|
||||
@opindex mno-cond-exec
|
||||
Disable ARCompact specific pass to generate conditional execution instructions.
|
||||
Disable the ARCompact-specific pass to generate conditional
|
||||
execution instructions.
|
||||
|
||||
Due to delay slot scheduling and interactions between operand numbers,
|
||||
literal sizes, instruction lengths, and the support for conditional execution,
|
||||
the target-independent pass to generate conditional execution is often lacking,
|
||||
so the ARC port has kept a special pass around that tries to find more
|
||||
conditional execution generating opportunities after register allocation,
|
||||
conditional execution generation opportunities after register allocation,
|
||||
branch shortening, and delay slot scheduling have been done. This pass
|
||||
generally, but not always, improves performance and code size, at the cost of
|
||||
extra compilation time, which is why there is an option to switch it off.
|
||||
@ -14719,11 +14715,11 @@ offset range because they are conditionalized, you should consider using
|
||||
|
||||
@item -mearly-cbranchsi
|
||||
@opindex mearly-cbranchsi
|
||||
Enable pre-reload use of the cbranchsi pattern.
|
||||
Enable pre-reload use of the @code{cbranchsi} pattern.
|
||||
|
||||
@item -mexpand-adddi
|
||||
@opindex mexpand-adddi
|
||||
Expand @code{adddi3} and @code{subdi3} at rtl generation time into
|
||||
Expand @code{adddi3} and @code{subdi3} at RTL generation time into
|
||||
@code{add.f}, @code{adc} etc.
|
||||
|
||||
@item -mindexed-loads
|
||||
@ -14767,17 +14763,19 @@ while increasing the instruction count.
|
||||
|
||||
@item -mq-class
|
||||
@opindex mq-class
|
||||
Enable 'q' instruction alternatives.
|
||||
Enable @samp{q} instruction alternatives.
|
||||
This is the default for @option{-Os}.
|
||||
|
||||
@item -mRcq
|
||||
@opindex mRcq
|
||||
Enable Rcq constraint handling - most short code generation depends on this.
|
||||
Enable @samp{Rcq} constraint handling.
|
||||
Most short code generation depends on this.
|
||||
This is the default.
|
||||
|
||||
@item -mRcw
|
||||
@opindex mRcw
|
||||
Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
|
||||
Enable @samp{Rcw} constraint handling.
|
||||
Most ccfsm condexec mostly depends on this.
|
||||
This is the default.
|
||||
|
||||
@item -msize-level=@var{level}
|
||||
@ -14811,22 +14809,22 @@ Supported values for @var{cpu} are
|
||||
|
||||
@table @samp
|
||||
@item ARC600
|
||||
Tune for ARC600 cpu.
|
||||
Tune for ARC600 CPU.
|
||||
|
||||
@item ARC601
|
||||
Tune for ARC601 cpu.
|
||||
Tune for ARC601 CPU.
|
||||
|
||||
@item ARC700
|
||||
Tune for ARC700 cpu with standard multiplier block.
|
||||
Tune for ARC700 CPU with standard multiplier block.
|
||||
|
||||
@item ARC700-xmac
|
||||
Tune for ARC700 cpu with XMAC block.
|
||||
Tune for ARC700 CPU with XMAC block.
|
||||
|
||||
@item ARC725D
|
||||
Tune for ARC725D cpu.
|
||||
Tune for ARC725D CPU.
|
||||
|
||||
@item ARC750D
|
||||
Tune for ARC750D cpu.
|
||||
Tune for ARC750D CPU.
|
||||
|
||||
@end table
|
||||
|
||||
@ -14860,19 +14858,19 @@ Obsolete FPX.
|
||||
@opindex mbig-endian
|
||||
@itemx -EB
|
||||
@opindex EB
|
||||
Compile code for big endian targets. Use of these options is now
|
||||
deprecated. Users wanting big-endian code, should use the
|
||||
@w{@code{arceb-elf32}} and @w{@code{arceb-linux-uclibc}} targets when
|
||||
building the tool chain, for which big-endian is the default.
|
||||
Compile code for big-endian targets. Use of these options is now
|
||||
deprecated. Big-endian code is supported by configuring GCC to build
|
||||
@w{@code{arceb-elf32}} and @w{@code{arceb-linux-uclibc}} targets,
|
||||
for which big endian is the default.
|
||||
|
||||
@item -mlittle-endian
|
||||
@opindex mlittle-endian
|
||||
@itemx -EL
|
||||
@opindex EL
|
||||
Compile code for little endian targets. Use of these options is now
|
||||
deprecated. Users wanting little-endian code should use the
|
||||
@w{@code{arc-elf32}} and @w{@code{arc-linux-uclibc}} targets when
|
||||
building the tool chain, for which little-endian is the default.
|
||||
Compile code for little-endian targets. Use of these options is now
|
||||
deprecated. Little-endian code is supported by configuring GCC to build
|
||||
@w{@code{arc-elf32}} and @w{@code{arc-linux-uclibc}} targets,
|
||||
for which little endian is the default.
|
||||
|
||||
@item -mbarrel_shifter
|
||||
@opindex mbarrel_shifter
|
||||
@ -14914,7 +14912,7 @@ Replaced by @option{-mspfp-fast}.
|
||||
@opindex mtune
|
||||
Values @samp{arc600}, @samp{arc601}, @samp{arc700} and
|
||||
@samp{arc700-xmac} for @var{cpu} are replaced by @samp{ARC600},
|
||||
@samp{ARC601}, @samp{ARC700} and @samp{ARC700-xmac} respectively
|
||||
@samp{ARC601}, @samp{ARC700} and @samp{ARC700-xmac} respectively.
|
||||
|
||||
@item -multcost=@var{num}
|
||||
@opindex multcost
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user