mirror/gcc
2
0
Fork 0
mirror of git://gcc.gnu.org/git/gcc.git synced 2025-03-09 19:17:24 +08:00
Code Issues Packages Projects Releases Wiki Activity

ia64.md (*ptr_extend_plus_1, [...]): New.

Browse Source 
* config/ia64/ia64.md (*ptr_extend_plus_1, *ptr_extend_plus_2): New.
        * config/ia64/ia64.c (basereg_operand): New.
        * config/ia64/ia64-protos.h (basereg_operand): Declare.
        * config/ia64/ia64.h (PREDICATE_CODES): Add basereg_operand.

From-SVN: r51564
This commit is contained in:
Steve Ellcey 2002-03-29 18:39:56 +00:00 committed by Richard Henderson
parent 6676c77f01
commit e206a74f52
5 changed files with 48 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2002-03-29 Steve Ellcey <sje@cup.hp.com>
* config/ia64/ia64.md (*ptr_extend_plus_1, *ptr_extend_plus_2): New.
* config/ia64/ia64.c (basereg_operand): New.
* config/ia64/ia64-protos.h (basereg_operand): Declare.
* config/ia64/ia64.h (PREDICATE_CODES): Add basereg_operand.
2002-03-29 Hans-Peter Nilsson <hp@bitrange.com>
* config/mmix/mmix.c (mmix_target_asm_function_prologue): Correct

1
gcc/config/ia64/ia64-protos.h
View File

@ -66,6 +66,7 @@ extern int ar_pfs_reg_operand PARAMS((rtx, enum machine_mode));
extern int general_tfmode_operand PARAMS((rtx, enum machine_mode));
extern int destination_tfmode_operand PARAMS((rtx, enum machine_mode));
extern int tfreg_or_fp01_operand PARAMS((rtx, enum machine_mode));
extern int basereg_operand PARAMS((rtx, enum machine_mode));
extern int ia64_move_ok PARAMS((rtx, rtx));
extern int ia64_depz_field_mask PARAMS((rtx, rtx));

15
gcc/config/ia64/ia64.c
View File

@ -864,6 +864,21 @@ tfreg_or_fp01_operand (op, mode)
return 0;
return fr_reg_or_fp01_operand (op, mode);
}
/* Return 1 if OP is valid as a base register in a reg + offset address. */
int
basereg_operand (op, mode)
rtx op;
enum machine_mode mode;
{
/* ??? Should I copy the flag_omit_frame_pointer and cse_not_expected
checks from pa.c basereg_operand as well? Seems to be OK without them
in test runs. */
return (register_operand (op, mode) &&
REG_POINTER ((GET_CODE (op) == SUBREG) ? SUBREG_REG (op) : op));
}
/* Return 1 if the operands of a move are ok. */

3
gcc/config/ia64/ia64.h
View File

@ -2351,7 +2351,8 @@ do { \
{ "ar_pfs_reg_operand", {REG}}, \
{ "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
{ "destination_tfmode_operand", {SUBREG, REG, MEM}}, \
{ "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}},
{ "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \
{ "basereg_operand", {SUBREG, REG}},
/* An alias for a machine mode name. This is the machine mode that elements of
a jump-table should have. */

23
gcc/config/ia64/ia64.md
View File

@ -5303,6 +5303,29 @@
"addp4 %0 = 0,%1"
[(set_attr "itanium_class" "ialu")])
;;
;; Optimizations for ptr_extend
(define_insn "*ptr_extend_plus_1"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(unspec:DI
[(plus:SI (match_operand:SI 1 "basereg_operand" "r")
(match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
24))]
""
"addp4 %0 = %2, %1"
[(set_attr "itanium_class" "ialu")])
(define_insn "*ptr_extend_plus_2"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
(unspec:DI
[(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
(match_operand:SI 2 "basereg_operand" "r"))]
24))]
""
"addp4 %0 = %1, %2"
[(set_attr "itanium_class" "ialu")])
;;
;; As USE insns aren't meaningful after reload, this is used instead
;; to prevent deleting instructions setting registers for EH handling