diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 31b7305b5f46..0581561f63dd 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2020-01-21  Kito Cheng  <kito.cheng@sifive.com>
+
+	PR target/93304
+	* config/riscv/riscv-protos.h (riscv_hard_regno_rename_ok): New.
+	* config/riscv/riscv.c (riscv_hard_regno_rename_ok): New.
+	* config/riscv/riscv.h (HARD_REGNO_RENAME_OK): Defined.
+
 2020-01-20  Wilco Dijkstra  <wdijkstr@arm.com>
 
 	* config/aarch64/aarch64.c (neoversen1_tunings): Set jump_align to 4.
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 26b811007a99..8cf9137b5e7e 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -89,4 +89,6 @@ extern void riscv_init_builtins (void);
 /* Routines implemented in riscv-common.c.  */
 extern std::string riscv_arch_str ();
 
+extern bool riscv_hard_regno_rename_ok (unsigned, unsigned);
+
 #endif /* ! GCC_RISCV_PROTOS_H */
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 320a70b9c863..573024074e3f 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -5021,6 +5021,19 @@ riscv_reorg (void)
     riscv_remove_unneeded_save_restore_calls ();
 }
 
+/* Return nonzero if register FROM_REGNO can be renamed to register
+   TO_REGNO.  */
+
+bool
+riscv_hard_regno_rename_ok (unsigned from_regno ATTRIBUTE_UNUSED,
+			    unsigned to_regno)
+{
+  /* Interrupt functions can only use registers that have already been
+     saved by the prologue, even if they would normally be
+     call-clobbered.  */
+  return !cfun->machine->interrupt_handler_p || df_regs_ever_live_p (to_regno);
+}
+
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 0bf3d2f81a81..19438e28fe88 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -926,4 +926,6 @@ extern unsigned riscv_stack_boundary;
 
 extern void riscv_remove_unneeded_save_restore_calls (void);
 
+#define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO)
+
 #endif /* ! GCC_RISCV_H */
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 452c16eb8c5e..fa457c86879e 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-01-21  Kito Cheng  <kito.cheng@sifive.com>
+
+	PR target/93304
+	* gcc.target/riscv/pr93304.c: New test.
+
 2020-01-20  Martin Sebor  <msebor@redhat.com>
 
 	PR testsuite/92829
diff --git a/gcc/testsuite/gcc.target/riscv/pr93304.c b/gcc/testsuite/gcc.target/riscv/pr93304.c
new file mode 100644
index 000000000000..f771e4859a96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr93304.c
@@ -0,0 +1,19 @@
+/* Verify the regrename won't rename registers to register which never used
+   before.  */
+/* { dg-do compile } */
+/* { dg-options "-O -frename-registers" } */
+
+static unsigned _t = 0;
+
+void __attribute__ ((interrupt))
+foo (void)
+{
+  _t++;
+}
+
+/* Register rename will try to use registers from the lower register
+   regradless of the REG_ALLOC_ORDER.
+   In theory, t0-t6 should not used in such small program if regrename
+   not executed incorrectly, because a5-a0 has higher priority in
+   REG_ALLOC_ORDER.  */
+/* { dg-final { scan-assembler-not "t\[0-6\]" } } */