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aarch64: Fix ICE due to aarch64_gen_compare_reg_maybe_ze [PR94435]

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The following testcase ICEs, because aarch64_gen_compare_reg_maybe_ze emits
invalid RTL.
For y_mode [QH]Imode it expects y to be of that mode (or CONST_INT that fits
into that mode) and x being SImode; for non-CONST_INT y it zero extends y
into SImode and compares that against x, for CONST_INT y it zero extends y
into SImode.  The problem is that when the zero extended constant isn't
usable directly, it forces it into a REG, but with y_mode mode, and then
compares against y.  That is wrong, because it should force it into a SImode
REG and compare that way.

2020-04-02  Jakub Jelinek  <jakub@redhat.com>

	PR target/94435
	* config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): For
	y_mode E_[QH]Imode and y being a CONST_INT, change y_mode to SImode.

	* gcc.target/aarch64/pr94435.c: New test.
This commit is contained in:
Jakub Jelinek 2020-04-02 12:57:11 +02:00
parent 66e327517b
commit df562b12d9
2 changed files with 29 additions and 1 deletions
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5
gcc/config/aarch64/aarch64.c
View File

@ -2371,7 +2371,10 @@ aarch64_gen_compare_reg_maybe_ze (RTX_CODE code, rtx x, rtx y,
if (y_mode == E_QImode || y_mode == E_HImode)
{
if (CONST_INT_P (y))
y = GEN_INT (INTVAL (y) & GET_MODE_MASK (y_mode));
{
y = GEN_INT (INTVAL (y) & GET_MODE_MASK (y_mode));
y_mode = SImode;
}
else
{
rtx t, cc_reg;

25
gcc/testsuite/gcc.target/aarch64/pr94435.c Normal file
View File

@ -0,0 +1,25 @@
/* PR target/94435 */
/* { dg-do compile } */
/* { dg-options "-march=armv8-a+nolse -moutline-atomics" } */
int b, c, d, e, f, h;
short g;
int foo (int) __attribute__ ((__const__));
void
bar (void)
{
while (1)
{
while (1)
{
__atomic_load_n (&e, 0);
if (foo (2))
__sync_val_compare_and_swap (&c, 0, f);
b = 1;
if (h == e)
break;
}
__sync_val_compare_and_swap (&g, -1, f);
}
}