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mn10300: Remove bset/bclr patterns.

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These instructions do not use normal addressing modes and are
incorrectly implemented for that.  Corrections to legitimate
addresses expose problems here.

Delete them for now.  To be re-instated later in the form of
atomic operation builtins.

From-SVN: r168676
This commit is contained in:
Richard Henderson 2011-01-11 10:38:48 -08:00 committed by Richard Henderson
parent 85a337b58a
commit df37c0236d
6 changed files with 11 additions and 332 deletions
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9
gcc/ChangeLog
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@ -1,5 +1,14 @@
2011-01-11 Richard Henderson <rth@redhat.com>
* config/mn10300/constraints.md ("R", "T"): Remove constraints.
* config/mn10300/mn10300.c (mn10300_mask_ok_for_mem_btst): Remove.
* config/mn10300/mn10300-protos.h: Update.
* config/mn10300/mn10300.md (movsi_internal): Don't use "R".
(*byte_clear, *byte_set, *bit_clear1, *bit_clear2, *bit_set): Remove.
(iorqi3, *am33_iorqi3, *mn10300_iorqi3): Remove.
(*test_int_bitfield, *test_byte_bitfield): Remove.
(*bit_test, *subreg_bit_test): Remove.
* config/mn10300/constraints.md ("c"): Rename from "A".
("A", "D"): New constraint letters.
* config/mn10300/mn10300.md (fmasf4): Use the "c" constraint.

23
gcc/config/mn10300/constraints.md
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@ -49,29 +49,6 @@
(and (match_code "mem")
(match_test "!CONSTANT_ADDRESS_P (XEXP (op, 0))")))
(define_memory_constraint "R"
"@internal"
(and (match_code "mem")
(match_test "mode == QImode")
(ior (match_test "CONSTANT_ADDRESS_P (XEXP (op, 0))")
(and (match_test "GET_CODE (XEXP (op, 0)) == REG")
(match_test "REG_OK_FOR_BIT_BASE_P (XEXP (op, 0))")
(match_test "XEXP (op, 0) != stack_pointer_rtx"))
(and (match_test "GET_CODE (XEXP (op, 0)) == PLUS")
(match_test "GET_CODE (XEXP (XEXP (op, 0), 0)) == REG")
(match_test "REG_OK_FOR_BIT_BASE_P (XEXP (XEXP (op, 0), 0))")
(match_test "XEXP (XEXP (op, 0), 0) != stack_pointer_rtx")
(match_test "GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT")
(match_test "INT_8_BITS (INTVAL (XEXP (XEXP (op, 0), 1)))")))))
(define_memory_constraint "T"
"@internal"
(and (match_code "mem")
(match_test "mode == QImode")
(and (match_test "GET_CODE (XEXP (op, 0)) == REG")
(match_test "REG_OK_FOR_BIT_BASE_P (XEXP (op, 0))")
(match_test "XEXP (op, 0) != stack_pointer_rtx"))))
(define_constraint "S"
"@internal"
(if_then_else (match_test "flag_pic")

1
gcc/config/mn10300/mn10300-protos.h
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@ -46,7 +46,6 @@ extern int mn10300_can_use_return_insn (void);
extern void mn10300_expand_prologue (void);
extern void mn10300_expand_epilogue (void);
extern int mn10300_initial_offset (int, int);
extern int mn10300_mask_ok_for_mem_btst (int, int);
#undef Mmode
#undef Cstar

21
gcc/config/mn10300/mn10300.c
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@ -1768,27 +1768,6 @@ mn10300_output_cmp (rtx operand, rtx insn)
return "cmp 0,%0";
}
/* Similarly, but when using a zero_extract pattern for a btst where
the source operand might end up in memory. */
int
mn10300_mask_ok_for_mem_btst (int len, int bit)
{
unsigned int mask = 0;
while (len > 0)
{
mask |= (1 << bit);
bit++;
len--;
}
/* MASK must bit into an 8bit value. */
return (((mask & 0xff) == mask)
|| ((mask & 0xff00) == mask)
|| ((mask & 0xff0000) == mask)
|| ((mask & 0xff000000) == mask));
}
/* Return 1 if X contains a symbolic expression. We know these
expressions will have one of a few well defined forms, so
we need only check those forms. */

277
gcc/config/mn10300/mn10300.md
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@ -490,9 +490,9 @@
(define_insn "*movsi_internal"
[(set (match_operand:SI 0 "nonimmediate_operand"
"=dax, dax, m, dax, axR, !*y")
"=dax, dax, m, dax, ax,!*y")
(match_operand:SI 1 "general_operand"
"0, Idax, dax, im, !*y, axR"))
"0, Idax, dax, im, !*y, ax"))
]
"register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode)"
@ -1657,279 +1657,6 @@
""
"not %0"
)
;; -----------------------------------------------------------------
;; BIT FIELDS
;; -----------------------------------------------------------------
;; These set/clear memory in byte sized chunks.
;;
;; They are no smaller/faster than loading the value into a register
;; and storing the register, but they don't need a scratch register
;; which may allow for better code generation.
(define_insn "*byte_clear"
[(set (match_operand:QI 0 "nonimmediate_operand" "=R,d") (const_int 0))
(clobber (reg:CC CC_REG))
]
"(! MEM_P (operands[0])) || (! MEM_VOLATILE_P (operands[0])
&& GET_CODE (XEXP (operands[0], 0)) != PLUS)"
"@
bclr 255,%A0
clr %0"
[(set_attr_alternative "timings"
[(if_then_else (eq_attr "cpu" "am34")
(const_int 66) (const_int 77))
(const_int 11)
])
]
)
(define_insn "*byte_set"
[(set (match_operand:QI 0 "nonimmediate_operand" "=R,d") (const_int -1))
(clobber (reg:CC CC_REG))
]
"(! MEM_P (operands[0])) || (! MEM_VOLATILE_P (operands[0])
&& GET_CODE (XEXP (operands[0], 0)) != PLUS)"
"@
bset 255,%A0
mov -1,%0"
[(set_attr_alternative "timings"
[(if_then_else (eq_attr "cpu" "am34")
(const_int 66) (const_int 77))
(const_int 11)
])
]
)
(define_insn "*bit_clear1"
[(set (match_operand:QI 0 "nonimmediate_operand" "+R,d")
(subreg:QI
(and:SI (subreg:SI (match_dup 0) 0)
(match_operand:SI 1 "const_int_operand" "i,i")) 0))
(clobber (reg:CC CC_REG))
]
""
"@
bclr %N1,%A0
and %1,%0"
[(set_attr_alternative "timings"
[(if_then_else (eq_attr "cpu" "am34")
(const_int 66) (const_int 77))
(const_int 11)
])
]
)
(define_insn "*bit_clear2"
[(set (match_operand:QI 0 "memory_operand" "=R,T")
(and:QI
(match_dup 0)
(not:QI (match_operand:QI 1 "nonmemory_operand" "i,d"))))
(clobber (reg:CC CC_REG))
]
""
"@
bclr %U1,%A0
bclr %1,%0"
[(set_attr_alternative "timings"
[(if_then_else (eq_attr "cpu" "am34")
(const_int 66) (const_int 77))
(const_int 66)
])
]
)
(define_insn "*bit_set"
[(set (match_operand:QI 0 "nonimmediate_operand" "+R,d")
(subreg:QI
(ior:SI (subreg:SI (match_dup 0) 0)
(match_operand:SI 1 "const_int_operand" "i,i")) 0))
(clobber (reg:CC CC_REG))
]
""
"@
bset %U1,%A0
or %1,%0"
[(set_attr_alternative "timings"
[(if_then_else (eq_attr "cpu" "am34")
(const_int 66) (const_int 77))
(const_int 11)
])
]
)
(define_expand "iorqi3"
[(parallel [(set (match_operand:QI 0 "nonimmediate_operand")
(ior:QI (match_operand:QI 1 "nonimmediate_operand")
(match_operand:QI 2 "nonmemory_operand")))
(clobber (reg:CC CC_REG))
])
]
""
"")
(define_insn "*am33_iorqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "=R,T,r")
(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
;; This constraint should really be nonmemory_operand,
;; but making it general_operand, along with the
;; condition that not both input operands are MEMs,
;; helps combine do a better job.
(match_operand:QI 2 "general_operand" "i,d,ir")))
(clobber (reg:CC CC_REG))
]
"TARGET_AM33 &&
((! MEM_P (operands[2])) || (! MEM_P (operands[1])))"
"@
bset %U2,%A0
bset %2,%0
or %2,%0"
[(set_attr_alternative "timings"
[(if_then_else (eq_attr "cpu" "am34")
(const_int 66) (const_int 77))
(const_int 66)
(const_int 11)
])
]
)
(define_insn "*mn10300_iorqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "=R,T,d")
(ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
;; This constraint should really be nonmemory_operand,
;; but making it general_operand, along with the
;; condition that not both input operands are MEMs,
;; helps combine do a better job.
(match_operand:QI 2 "general_operand" "i,d,id")))
(clobber (reg:CC CC_REG))
]
"(! MEM_P (operands[2])) || (! MEM_P (operands[1]))"
"@
bset %U2,%A0
bset %2,%0
or %2,%0"
[(set_attr_alternative "timings"
[(if_then_else (eq_attr "cpu" "am34")
(const_int 66) (const_int 77))
(const_int 66)
(const_int 11)
])
]
)
(define_insn "*test_int_bitfield"
[(set (reg:CC CC_REG)
(compare (zero_extract:SI (match_operand:SI 0 "register_operand" "dx")
(match_operand 1 "const_int_operand" "")
(match_operand 2 "const_int_operand" ""))
(const_int 0)))]
""
"*
{
int len = INTVAL (operands[1]);
int bit = INTVAL (operands[2]);
int mask = 0;
rtx xoperands[2];
while (len > 0)
{
mask |= (1 << bit);
bit++;
len--;
}
xoperands[0] = operands[0];
xoperands[1] = GEN_INT (trunc_int_for_mode (mask, SImode));
output_asm_insn (\"btst %1,%0\", xoperands);
return \"\";
}"
)
(define_insn "*test_byte_bitfield"
[(set (reg:CC CC_REG)
(compare (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "R,dx")
(match_operand 1 "const_int_operand" "")
(match_operand 2 "const_int_operand" ""))
(const_int 0)))]
"mn10300_mask_ok_for_mem_btst (INTVAL (operands[1]), INTVAL (operands[2]))"
"*
{
int len = INTVAL (operands[1]);
int bit = INTVAL (operands[2]);
int mask = 0;
rtx xoperands[2];
while (len > 0)
{
mask |= (1 << bit);
bit++;
len--;
}
/* If the source operand is not a reg (i.e. it is memory), then extract the
bits from mask that we actually want to test. Note that the mask will
never cross a byte boundary. */
if (!REG_P (operands[0]))
{
if (mask & 0xff)
mask = mask & 0xff;
else if (mask & 0xff00)
mask = (mask >> 8) & 0xff;
else if (mask & 0xff0000)
mask = (mask >> 16) & 0xff;
else if (mask & 0xff000000)
mask = (mask >> 24) & 0xff;
}
xoperands[0] = operands[0];
xoperands[1] = GEN_INT (trunc_int_for_mode (mask, SImode));
if (REG_P (operands[0]))
output_asm_insn (\"btst %1,%0\", xoperands);
else
output_asm_insn (\"btst %U1,%A0\", xoperands);
return \"\";
}"
[(set_attr_alternative "timings"
[(if_then_else (eq_attr "cpu" "am34")
(const_int 11) (const_int 22))
(if_then_else (eq_attr "cpu" "am34")
(const_int 44) (const_int 55))
])
]
)
(define_insn "*bit_test"
[(set (reg:CC CC_REG)
(compare (and:SI (match_operand:SI 0 "register_operand" "dx")
(match_operand:SI 1 "const_int_operand" ""))
(const_int 0)))
]
""
"btst %1,%0"
[(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
(const_int 11) (const_int 22)))]
)
(define_insn "*subreg_bit_test"
[(set (reg:CC CC_REG)
(compare (and:SI
(subreg:SI (match_operand:QI 0 "nonimmediate_operand" "R,dx") 0)
(match_operand:SI 1 "const_8bit_operand" ""))
(const_int 0)))]
""
"@
btst %U1,%A0
btst %1,%0"
[(set_attr_alternative "timings"
[(if_then_else (eq_attr "cpu" "am34")
(const_int 44) (const_int 55))
(if_then_else (eq_attr "cpu" "am34")
(const_int 11) (const_int 22))
])
]
)
;; ----------------------------------------------------------------------
;; COMPARE AND BRANCH INSTRUCTIONS

12
gcc/config/mn10300/predicates.md
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@ -25,18 +25,6 @@
return (op == CONST1_RTX (SFmode));
})
;; Return 1 if X is a CONST_INT that is only 8 bits wide. This is
;; used for the btst insn which may examine memory or a register (the
;; memory variant only allows an unsigned 8-bit integer).
(define_predicate "const_8bit_operand"
(match_code "const_int")
{
return (GET_CODE (op) == CONST_INT
&& INTVAL (op) >= 0
&& INTVAL (op) < 256);
})
;; Return true if OP is a valid call operand.
(define_predicate "call_address_operand"