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[AArch64] Add banner comments to aarch64-sve2.md
This patch imposes the same sort of structure on aarch64-sve2.md as we already have for aarch64-sve.md, before it grows a lot more patterns. 2020-01-09 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/aarch64-sve2.md: Add banner comments. (<su>mulh<r>s<mode>3): Move further up file. (<su>mull<bt><Vwide>, <r>shrnb<mode>, <r>shrnt<mode>) (*aarch64_sve2_sra<mode>): Move further down file. * config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too. From-SVN: r280058
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Richard Sandiford
Richard Sandiford
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gcc
@ -1,3 +1,11 @@
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2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/aarch64-sve2.md: Add banner comments.
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(<su>mulh<r>s<mode>3): Move further up file.
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(<su>mull<bt><Vwide>, <r>shrnb<mode>, <r>shrnt<mode>)
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(*aarch64_sve2_sra<mode>): Move further down file.
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* config/aarch64/t-aarch64 (s-check-sve-md): Check aarch64-sve2.md too.
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2020-01-09 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/iterators.md (SVE_WHILE): Add UNSPEC_WHILERW
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@ -18,6 +18,75 @@
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; The file is organised into the following sections (search for the full
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;; line):
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;;
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;; == Uniform binary arithmnetic
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;; ---- [INT] Scaled high-part multiplication
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;; ---- [INT] General binary arithmetic that maps to unspecs
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;;
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;; == Uniform ternary arithmnetic
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;; ---- [INT] Ternary logic operations
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;; ---- [INT] Shift-and-accumulate operations
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;;
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;; == Extending arithmetic
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;; ---- [INT] Long binary arithmetic
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;;
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;; == Narrowing arithnetic
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;; ---- [INT] Narrowing right shifts
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;;
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;; == General
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;; ---- Check for aliases between pointers
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;; =========================================================================
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;; == Uniform binary arithmnetic
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;; =========================================================================
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;; -------------------------------------------------------------------------
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;; ---- [INT] Scaled high-part multiplication
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;; -------------------------------------------------------------------------
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;; The patterns in this section are synthetic.
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;; -------------------------------------------------------------------------
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;; Unpredicated integer multiply-high-with-(round-and-)scale.
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(define_expand "<su>mulh<r>s<mode>3"
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[(set (match_operand:SVE_FULL_BHSI 0 "register_operand")
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(unspec:SVE_FULL_BHSI
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[(match_dup 3)
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(unspec:SVE_FULL_BHSI
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[(match_operand:SVE_FULL_BHSI 1 "register_operand")
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(match_operand:SVE_FULL_BHSI 2 "register_operand")]
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MULHRS)]
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UNSPEC_PRED_X))]
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"TARGET_SVE2"
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{
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operands[3] = aarch64_ptrue_reg (<VPRED>mode);
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rtx prod_b = gen_reg_rtx (<VWIDE>mode);
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rtx prod_t = gen_reg_rtx (<VWIDE>mode);
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emit_insn (gen_<su>mullb<Vwide> (prod_b, operands[1], operands[2]));
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emit_insn (gen_<su>mullt<Vwide> (prod_t, operands[1], operands[2]));
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rtx shift = GEN_INT (GET_MODE_UNIT_BITSIZE (<MODE>mode) - 1);
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emit_insn (gen_<r>shrnb<mode> (operands[0], prod_b, shift));
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emit_insn (gen_<r>shrnt<mode> (operands[0], operands[0], prod_t, shift));
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DONE;
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}
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)
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;; -------------------------------------------------------------------------
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;; ---- [INT] General binary arithmetic that maps to unspecs
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;; -------------------------------------------------------------------------
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;; Includes:
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;; - SHADD
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;; - SHSUB
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;; - SRHADD
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;; - UHADD
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;; - UHSUB
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;; - URHADD
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;; -------------------------------------------------------------------------
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;; Integer average (floor).
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(define_expand "<u>avg<mode>3_floor"
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[(set (match_operand:SVE_FULL_I 0 "register_operand")
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@ -67,85 +136,20 @@
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[(set_attr "movprfx" "*,yes")]
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)
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;; Multiply long top / bottom.
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(define_insn "<su>mull<bt><Vwide>"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(unspec:<VWIDE>
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[(match_operand:SVE_FULL_BHSI 1 "register_operand" "w")
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(match_operand:SVE_FULL_BHSI 2 "register_operand" "w")]
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MULLBT))]
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"TARGET_SVE2"
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"<su>mull<bt>\t%0.<Vewtype>, %1.<Vetype>, %2.<Vetype>"
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)
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;; =========================================================================
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;; == Uniform ternary arithmnetic
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;; =========================================================================
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;; (Rounding) Right shift narrow bottom.
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(define_insn "<r>shrnb<mode>"
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[(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w")
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(unspec:SVE_FULL_BHSI
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[(match_operand:<VWIDE> 1 "register_operand" "w")
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(match_operand 2 "aarch64_simd_shift_imm_offset_<Vel>" "")]
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SHRNB))]
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"TARGET_SVE2"
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"<r>shrnb\t%0.<Vetype>, %1.<Vewtype>, #%2"
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)
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;; (Rounding) Right shift narrow top.
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(define_insn "<r>shrnt<mode>"
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[(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w")
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(unspec:SVE_FULL_BHSI
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[(match_operand:SVE_FULL_BHSI 1 "register_operand" "0")
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(match_operand:<VWIDE> 2 "register_operand" "w")
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(match_operand 3 "aarch64_simd_shift_imm_offset_<Vel>" "i")]
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SHRNT))]
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"TARGET_SVE2"
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"<r>shrnt\t%0.<Vetype>, %2.<Vewtype>, #%3"
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)
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;; Unpredicated integer multiply-high-with-(round-and-)scale.
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(define_expand "<su>mulh<r>s<mode>3"
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[(set (match_operand:SVE_FULL_BHSI 0 "register_operand")
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(unspec:SVE_FULL_BHSI
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[(match_dup 3)
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(unspec:SVE_FULL_BHSI
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[(match_operand:SVE_FULL_BHSI 1 "register_operand")
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(match_operand:SVE_FULL_BHSI 2 "register_operand")]
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MULHRS)]
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UNSPEC_PRED_X))]
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"TARGET_SVE2"
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{
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operands[3] = aarch64_ptrue_reg (<VPRED>mode);
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rtx prod_b = gen_reg_rtx (<VWIDE>mode);
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rtx prod_t = gen_reg_rtx (<VWIDE>mode);
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emit_insn (gen_<su>mullb<Vwide> (prod_b, operands[1], operands[2]));
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emit_insn (gen_<su>mullt<Vwide> (prod_t, operands[1], operands[2]));
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rtx shift = GEN_INT (GET_MODE_UNIT_BITSIZE (<MODE>mode) - 1);
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emit_insn (gen_<r>shrnb<mode> (operands[0], prod_b, shift));
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emit_insn (gen_<r>shrnt<mode> (operands[0], operands[0], prod_t, shift));
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DONE;
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}
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)
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;; Unpredicated signed / unsigned shift-right accumulate.
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(define_insn_and_rewrite "*aarch64_sve2_sra<mode>"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w")
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(plus:SVE_FULL_I
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(unspec:SVE_FULL_I
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[(match_operand 4)
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(SHIFTRT:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand" "w")
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(match_operand:SVE_FULL_I 3 "aarch64_simd_rshift_imm" "Dr"))]
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UNSPEC_PRED_X)
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(match_operand:SVE_FULL_I 1 "register_operand" "0")))]
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"TARGET_SVE2"
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"<sra_op>sra\t%0.<Vetype>, %2.<Vetype>, #%3"
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"&& !CONSTANT_P (operands[4])"
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{
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operands[4] = CONSTM1_RTX (<VPRED>mode);
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}
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)
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;; -------------------------------------------------------------------------
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;; ---- [INT] Ternary logic operations
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;; -------------------------------------------------------------------------
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;; Includes:
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;; - BSL
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;; - BSL1N
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;; - BSL2N
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;; - EOR3
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;; - NBSL
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;; -------------------------------------------------------------------------
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;; Unpredicated 3-way exclusive OR.
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(define_insn "*aarch64_sve2_eor3<mode>"
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@ -332,6 +336,106 @@
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[(set_attr "movprfx" "*,yes")]
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)
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;; -------------------------------------------------------------------------
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;; ---- [INT] Shift-and-accumulate operations
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;; -------------------------------------------------------------------------
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;; Includes:
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;; - SSRA
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;; - USRA
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;; -------------------------------------------------------------------------
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;; Unpredicated signed / unsigned shift-right accumulate.
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(define_insn_and_rewrite "*aarch64_sve2_sra<mode>"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w")
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(plus:SVE_FULL_I
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(unspec:SVE_FULL_I
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[(match_operand 4)
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(SHIFTRT:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand" "w")
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(match_operand:SVE_FULL_I 3 "aarch64_simd_rshift_imm" "Dr"))]
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UNSPEC_PRED_X)
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(match_operand:SVE_FULL_I 1 "register_operand" "0")))]
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"TARGET_SVE2"
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"<sra_op>sra\t%0.<Vetype>, %2.<Vetype>, #%3"
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"&& !CONSTANT_P (operands[4])"
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{
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operands[4] = CONSTM1_RTX (<VPRED>mode);
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}
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)
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;; =========================================================================
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;; == Extending arithmetic
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;; =========================================================================
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;; -------------------------------------------------------------------------
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;; ---- [INT] Long binary arithmetic
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;; -------------------------------------------------------------------------
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;; Includes:
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;; - SMULLB
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;; - SMULLT
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;; - UMULLB
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;; - UMULLT
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;; -------------------------------------------------------------------------
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;; Multiply long top / bottom.
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(define_insn "<su>mull<bt><Vwide>"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(unspec:<VWIDE>
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[(match_operand:SVE_FULL_BHSI 1 "register_operand" "w")
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(match_operand:SVE_FULL_BHSI 2 "register_operand" "w")]
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MULLBT))]
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"TARGET_SVE2"
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"<su>mull<bt>\t%0.<Vewtype>, %1.<Vetype>, %2.<Vetype>"
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)
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;; =========================================================================
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;; == Narrowing arithnetic
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;; =========================================================================
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;; -------------------------------------------------------------------------
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;; ---- [INT] Narrowing right shifts
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;; -------------------------------------------------------------------------
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;; Includes:
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;; - RSHRNB
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;; - RSHRNT
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;; - SHRNB
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;; - SHRNT
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;; -------------------------------------------------------------------------
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;; (Rounding) Right shift narrow bottom.
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(define_insn "<r>shrnb<mode>"
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[(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w")
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(unspec:SVE_FULL_BHSI
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[(match_operand:<VWIDE> 1 "register_operand" "w")
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(match_operand 2 "aarch64_simd_shift_imm_offset_<Vel>" "")]
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SHRNB))]
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"TARGET_SVE2"
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"<r>shrnb\t%0.<Vetype>, %1.<Vewtype>, #%2"
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)
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;; (Rounding) Right shift narrow top.
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(define_insn "<r>shrnt<mode>"
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[(set (match_operand:SVE_FULL_BHSI 0 "register_operand" "=w")
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(unspec:SVE_FULL_BHSI
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[(match_operand:SVE_FULL_BHSI 1 "register_operand" "0")
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(match_operand:<VWIDE> 2 "register_operand" "w")
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(match_operand 3 "aarch64_simd_shift_imm_offset_<Vel>" "i")]
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SHRNT))]
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"TARGET_SVE2"
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"<r>shrnt\t%0.<Vetype>, %2.<Vewtype>, #%3"
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)
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;; =========================================================================
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;; == General
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;; =========================================================================
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;; -------------------------------------------------------------------------
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;; ---- Check for aliases between pointers
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;; -------------------------------------------------------------------------
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;; The patterns in this section are synthetic: WHILERW and WHILEWR are
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;; defined in aarch64-sve.md instead.
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;; -------------------------------------------------------------------------
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;; Use WHILERW and WHILEWR to accelerate alias checks. This is only
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;; possible if the accesses we're checking are exactly the same size
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;; as an SVE vector.
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@ -147,7 +147,10 @@ MULTILIB_DIRNAMES = $(subst $(comma), ,$(TM_MULTILIB_CONFIG))
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insn-conditions.md: s-check-sve-md
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s-check-sve-md: $(srcdir)/config/aarch64/check-sve-md.awk \
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$(srcdir)/config/aarch64/aarch64-sve.md
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$(srcdir)/config/aarch64/aarch64-sve.md \
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$(srcdir)/config/aarch64/aarch64-sve2.md
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$(AWK) -f $(srcdir)/config/aarch64/check-sve-md.awk \
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$(srcdir)/config/aarch64/aarch64-sve.md
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$(AWK) -f $(srcdir)/config/aarch64/check-sve-md.awk \
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$(srcdir)/config/aarch64/aarch64-sve2.md
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$(STAMP) s-check-sve-md
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