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m32r.c: Add support for m32rx processor.
* m32r.c: Add support for m32rx processor.
* m32r.h: Ditto.
* m32r.md: Ditto.
* t-m32r: Ditto.
* m32r-protos.h: Add prototypes for m32rx functions.
* doc/invoke.texi: Document -m32rx option.
Co-Authored-By: Andrew MacLeod <amacleod@redhat.com>
Co-Authored-By: Catherine Moore <clm@redhat.com>
Co-Authored-By: Michael Meissner <meissner@redhat.com>
Co-Authored-By: Nick Clifton <nickc@redhat.com>
Co-Authored-By: Richard Henderson <rth@redhat.com>
From-SVN: r46881
This commit is contained in:
Ben Elliston
Catherine Moore
parent
a3d87e92eb
commit
de41e41c42
@ -1,3 +1,17 @@
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2001-11-09 Ben Elliston <bje@redhat.com>
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Michael Meissner <meissner@redhat.com>
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Andrew MacLeod <amacleod@redhat.com>
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Richard Henderson <rth@redhat.com>
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Nick Clifton <nickc@redhat.com>
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Catherine Moore <clm@redhat.com>
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* m32r.c: Add support for m32rx processor.
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* m32r.h: Ditto.
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* m32r.md: Ditto.
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* t-m32r: Ditto.
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* m32r-protos.h: Add prototypes for m32rx functions.
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* doc/invoke.texi: Document -m32rx option.
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2001-11-09 Jakub Jelinek <jakub@redhat.com>
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* config/sparc/sparc.md (movdf): Avoid calling validize_mem during
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@ -90,6 +90,8 @@ extern int m32r_block_immediate_operand PARAMS ((rtx, Mmode));
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extern int extend_operand PARAMS ((rtx, Mmode));
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extern int reg_or_eq_int16_operand PARAMS ((rtx, Mmode));
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extern int int8_operand PARAMS ((rtx, Mmode));
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extern int reg_or_zero_operand PARAMS ((rtx, Mmode));
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#endif /* HAVE_MACHINE_MODES */
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#ifdef TREE_CODE
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@ -171,7 +171,7 @@ unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
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{
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T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
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T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
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S_MODES, C_MODES, A_MODES
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S_MODES, C_MODES, A_MODES, A_MODES
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};
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unsigned int m32r_mode_class [NUM_MACHINE_MODES];
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@ -462,6 +462,10 @@ m32r_encode_section_info (decl)
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strcpy (newstr + 1, str);
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*newstr = prefix;
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/* Note - we cannot leave the string in the ggc_alloc'ed space.
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It must reside in the stringtable's domain. */
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newstr = (char *) ggc_alloc_string (newstr, len + 2);
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XSTR (XEXP (rtl, 0), 0) = newstr;
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}
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}
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@ -734,6 +738,22 @@ reg_or_cmp_int16_operand (op, mode)
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return CMP_INT16_P (INTVAL (op));
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}
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/* Return true if OP is a register or the constant 0. */
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int
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reg_or_zero_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
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return register_operand (op, mode);
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if (GET_CODE (op) != CONST_INT)
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return 0;
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return INTVAL (op) == 0;
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}
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/* Return true if OP is a const_int requiring two instructions to load. */
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int
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@ -40,6 +40,58 @@ Boston, MA 02111-1307, USA. */
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#undef ENDFILE_SPEC
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#undef SUBTARGET_SWITCHES
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/* M32R/X overrides. */
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/* Print subsidiary information on the compiler version in use. */
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#define TARGET_VERSION fprintf (stderr, " (m32r/x)");
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/* Additional flags for the preprocessor. */
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#define CPP_CPU_SPEC "%{m32rx:-D__M32RX__} %{m32r:-U__M32RX__}"
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/* Assembler switches. */
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#define ASM_CPU_SPEC \
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"%{m32r} %{m32rx} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts"
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/* Use m32rx specific crt0/crtinit/crtfini files. */
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#define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}"
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#define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}"
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/* Extra machine dependent switches. */
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#define SUBTARGET_SWITCHES \
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{ "32rx", TARGET_M32RX_MASK, "Compile for the m32rx" }, \
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{ "32r", -TARGET_M32RX_MASK, "" },
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/* Define this macro as a C expression for the initializer of an array of
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strings to tell the driver program which options are defaults for this
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target and thus do not need to be handled specially when using
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`MULTILIB_OPTIONS'. */
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#define SUBTARGET_MULTILIB_DEFAULTS , "m32r"
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/* Number of additional registers the subtarget defines. */
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#define SUBTARGET_NUM_REGISTERS 1
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/* 1 for registers that cannot be allocated. */
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#define SUBTARGET_FIXED_REGISTERS , 1
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/* 1 for registers that are not available across function calls. */
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#define SUBTARGET_CALL_USED_REGISTERS , 1
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/* Order to allocate model specific registers. */
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#define SUBTARGET_REG_ALLOC_ORDER , 19
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/* Registers which are accumulators. */
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#define SUBTARGET_REG_CLASS_ACCUM 0x80000
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/* All registers added. */
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#define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM
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/* Additional accumulator registers. */
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#define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19)
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/* Define additional register names. */
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#define SUBTARGET_REGISTER_NAMES , "a1"
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/* end M32R/X overrides. */
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/* Print subsidiary information on the compiler version in use. */
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#ifndef TARGET_VERSION
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#define TARGET_VERSION fprintf (stderr, " (m32r)")
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@ -161,6 +213,12 @@ extern int target_flags;
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/* Target machine to compile for. */
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#define TARGET_M32R 1
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/* Support extended instruction set. */
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#define TARGET_M32RX_MASK (1 << 5)
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#define TARGET_M32RX (target_flags & TARGET_M32RX_MASK)
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#undef TARGET_M32R
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#define TARGET_M32R (! TARGET_M32RX)
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/* Macro to define tables used to set the flags.
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This is a list in braces of pairs in braces,
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each pair being { "NAME", VALUE }
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@ -513,7 +571,7 @@ extern enum m32r_sdata m32r_sdata;
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16 - arg pointer
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17 - carry flag
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18 - accumulator
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19 - accumulator 1 in the m32r/x
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By default, the extension registers are not available. */
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#ifndef SUBTARGET_FIXED_REGISTERS
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@ -2051,6 +2109,7 @@ enum m32r_function_type
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matched by the predicate. The list should have a trailing comma. */
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#define PREDICATE_CODES \
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{ "reg_or_zero_operand", { REG, SUBREG, CONST_INT }}, \
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{ "conditional_move_operand", { REG, SUBREG, CONST_INT }}, \
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{ "carry_compare_operand", { EQ, NE }}, \
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{ "eqne_comparison_operator", { EQ, NE }}, \
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@ -69,6 +69,26 @@
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(define_attr "m32r" "no,yes"
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(const (symbol_ref "(TARGET_M32R != 0)")))
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(define_attr "m32rx" "no,yes"
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(const (symbol_ref "(TARGET_M32RX != 0)")))
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(define_attr "m32rx_pipeline" "either,s,o,long,m32r"
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(cond [(eq_attr "m32rx" "no")
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(const_string "m32r")
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(eq_attr "insn_size" "!short")
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(const_string "long")]
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(cond [(eq_attr "type" "int2")
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(const_string "either")
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(eq_attr "type" "load2,store2,shift2,uncond_branch,branch,call")
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(const_string "o")
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(eq_attr "type" "mul2")
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(const_string "s")]
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(const_string "long"))))
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;; ::::::::::::::::::::
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;; ::
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@ -218,6 +238,36 @@
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3 0
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[(eq_attr "insn_size" "short")])
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(define_function_unit "left" 1 1
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(and (eq_attr "m32rx_pipeline" "o,either")
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(eq_attr "type" "!load2"))
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1 0
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[(eq_attr "insn_size" "long")])
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(define_function_unit "left" 1 1 ;; load delay of 1 clock for mem execution + 1 clock for WB
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(and (eq_attr "m32rx_pipeline" "o,either")
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(eq_attr "type" "load2"))
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3 0
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[(eq_attr "insn_size" "long")])
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(define_function_unit "right" 1 1
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(eq_attr "m32rx_pipeline" "s,either")
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1 0
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[(eq_attr "insn_size" "long")])
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(define_function_unit "long" 1 1
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(and (eq_attr "m32rx" "yes")
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(and (eq_attr "insn_size" "long")
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(eq_attr "type" "!load4,load8")))
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2 0
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[(eq_attr "insn_size" "short")])
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(define_function_unit "long" 1 1 ;; load delay of 1 clock for mem execution + 1 clock for WB
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(and (eq_attr "m32rx" "yes")
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(and (eq_attr "insn_size" "long")
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(eq_attr "type" "load4,load8")))
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3 0
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[(eq_attr "insn_size" "short")])
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;; Expand prologue as RTL
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(define_expand "prologue"
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@ -1126,14 +1176,25 @@
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DONE;
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}")
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(define_insn "cmp_eqsi_zero_insn"
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[(set (reg:SI 17)
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(eq:SI (match_operand:SI 0 "register_operand" "r,r")
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(match_operand:SI 1 "reg_or_zero_operand" "r,P")))]
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"TARGET_M32RX"
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"@
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cmpeq %0, %1
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cmpz %0"
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[(set_attr "type" "int4")
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(set_attr "length" "4")])
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;; The cmp_xxx_insn patterns set the condition bit to the result of the
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;; comparison. There isn't a "compare equal" instruction so cmp_eqsi_insn
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;; is quite inefficient. However, it is rarely used.
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(define_insn "cmp_eqsi_insn"
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[(set (reg:SI 17)
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(eq:SI (match_operand:SI 0 "register_operand" "r,r")
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(match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
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(eq:SI (match_operand:SI 0 "register_operand" "r,r")
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(match_operand:SI 1 "reg_or_cmp_int16_operand" "r,P")))
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(clobber (match_scratch:SI 2 "=&r,&r"))]
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""
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"*
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@ -1157,8 +1218,8 @@
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(define_insn "cmp_ltsi_insn"
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[(set (reg:SI 17)
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(lt:SI (match_operand:SI 0 "register_operand" "r,r")
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(match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
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(lt:SI (match_operand:SI 0 "register_operand" "r,r")
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(match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
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""
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"@
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cmp %0,%1
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@ -1168,8 +1229,8 @@
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(define_insn "cmp_ltusi_insn"
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[(set (reg:SI 17)
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(ltu:SI (match_operand:SI 0 "register_operand" "r,r")
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(match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
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(ltu:SI (match_operand:SI 0 "register_operand" "r,r")
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(match_operand:SI 1 "reg_or_int16_operand" "r,J")))]
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""
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"@
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cmpu %0,%1
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@ -1177,6 +1238,7 @@
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[(set_attr "type" "int2,int4")
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(set_attr "length" "2,4")])
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;; reg == small constant comparisons are best handled by putting the result
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;; of the comparison in a tmp reg and then using beqz/bnez.
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;; ??? The result register doesn't contain 0/STORE_FLAG_VALUE,
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@ -1448,7 +1510,7 @@
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""
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"*
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{
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const char *br,*invbr;
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char *br,*invbr;
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char asmtext[40];
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switch (GET_CODE (operands[1]))
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@ -1495,7 +1557,7 @@
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""
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"*
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{
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const char *br,*invbr;
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char *br,*invbr;
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char asmtext[40];
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switch (GET_CODE (operands[1]))
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@ -1550,6 +1612,14 @@
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if (! register_operand (op1, mode))
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op1 = force_reg (mode, op1);
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if (TARGET_M32RX)
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{
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if (! reg_or_zero_operand (op2, mode))
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op2 = force_reg (mode, op2);
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emit_insn (gen_seq_insn_m32rx (op0, op1, op2));
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DONE;
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}
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if (GET_CODE (op2) == CONST_INT && INTVAL (op2) == 0)
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{
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emit_insn (gen_seq_zero_insn (op0, op1));
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@ -1563,6 +1633,29 @@
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DONE;
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}")
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(define_insn "seq_insn_m32rx"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(eq:SI (match_operand:SI 1 "register_operand" "%r")
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(match_operand:SI 2 "reg_or_zero_operand" "rP")))
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(clobber (reg:SI 17))]
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"TARGET_M32RX"
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"#"
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[(set_attr "type" "multi")
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(set_attr "length" "6")])
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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(eq:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "reg_or_zero_operand" "")))
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(clobber (reg:SI 17))]
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"TARGET_M32RX"
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[(set (reg:SI 17)
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(eq:SI (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(reg:SI 17))]
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"")
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(define_insn "seq_zero_insn"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(eq:SI (match_operand:SI 1 "register_operand" "r")
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@ -36,17 +36,30 @@ crtfini.o: $(srcdir)/config/m32r/initfini.c $(GCC_PASSES) $(CONFIG_H)
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-DCRT_FINI -finhibit-size-directive -fno-inline-functions \
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-g0 -mmodel=medium -c $(srcdir)/config/m32r/initfini.c -o crtfini.o
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m32rx:
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mkdir $@
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m32rx/crtinit.o: m32rx $(srcdir)/config/m32r/initfini.c $(GCC_PASSES) $(CONFIG_H)
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$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(CRTSTUFF_T_CFLAGS) \
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-DCRT_INIT -finhibit-size-directive -fno-inline-functions \
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-g0 -mmodel=medium -c $(srcdir)/config/m32r/initfini.c -m32rx \
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-o m32rx/crtinit.o
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m32rx/crtfini.o: m32rx $(srcdir)/config/m32r/initfini.c $(GCC_PASSES) $(CONFIG_H)
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$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(CRTSTUFF_T_CFLAGS) \
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-DCRT_FINI -finhibit-size-directive -fno-inline-functions \
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-g0 -mmodel=medium -c $(srcdir)/config/m32r/initfini.c -m32rx \
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-o m32rx/crtfini.o
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# -mmodel={small,medium} requires separate libraries.
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# We don't build libraries for the large model, instead we use the medium
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# libraries. The only difference is that the large model can handle jumps
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# more than 26 signed bits away.
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MULTILIB_OPTIONS = mmodel=small/mmodel=medium
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MULTILIB_DIRNAMES = small medium
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MULTILIB_OPTIONS = mmodel=small/mmodel=medium m32r/m32rx
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MULTILIB_DIRNAMES = small medium m32r m32rx
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MULTILIB_MATCHES = mmodel?medium=mmodel?large
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# Set MULTILIB_EXTRA_OPTS so shipped libraries have small data in .sdata and
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# SHN_M32R_SCOMMON.
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# This is important for objects referenced in system header files.
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@ -402,7 +402,7 @@ in the following sections.
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@emph{M32R/D Options}
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@gccoptlist{
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-mcode-model=@var{model-type} -msdata=@var{sdata-type} @gol
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-mm32rx -mcode-model=@var{model-type} -msdata=@var{sdata-type} @gol
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-G @var{num}}
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@emph{M88K Options}
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@ -6227,6 +6227,10 @@ This option makes symbolic debugging impossible.
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These @option{-m} options are defined for Mitsubishi M32R/D architectures:
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@table @gcctabopt
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@item -mm32rx
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@opindex mm32rx
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Generate code for the M32R/X. The default is to generate code for the M32R.
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@item -mcode-model=small
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@opindex mcode-model=small
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Assume all objects live in the lower 16MB of memory (so that their addresses
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