mirror/gcc
2
0
Fork 0
mirror of git://gcc.gnu.org/git/gcc.git synced 2025-03-19 01:40:39 +08:00
Code Issues Packages Projects Releases Wiki Activity

config.gcc (ia64*-*-hpux*): Add extra_options.

Browse Source 
* config.gcc (ia64*-*-hpux*): Add extra_options.
        * config/ia64/hpux.h (SUBTARGET_SWITCHES): Remove.
        (TARGET_DEFAULT): Remove MASK_INLINE_FLOAT_DIV_THR.
        * config/ia64/ia64.c (ia64_fixed_range_string): Remove.
        (ia64_tls_size_string, ia64_tune_string): Remove.
        (ia64_tune): Init to PROCESSOR_ITANIUM2.
        (TARGET_DEFAULT_TARGET_FLAGS): New.
        (TARGET_HANDLE_OPTION): New.
        (ia64_override_options): Move options parsing ...
        (ia64_handle_option): ... here.  New.
        * config/ia64/ia64.h (target_flags, MASK_BIG_ENDIAN, MASK_GNU_AS,
        MASK_GNU_LD, MASK_NO_PIC, MASK_VOL_ASM_STOP, MASK_ILP32,
        MASK_REG_NAMES, MASK_NO_SDATA, MASK_CONST_GP, MASK_AUTO_PIC,
        MASK_INLINE_FLOAT_DIV_LAT, MASK_INLINE_FLOAT_DIV_THR,
        MASK_INLINE_INT_DIV_LAT, MASK_INLINE_INT_DIV_THR,
        MASK_INLINE_SQRT_LAT, MASK_INLINE_SQRT_THR, MASK_DWARF2_ASM,
        MASK_EARLY_STOP_BITS, TARGET_BIG_ENDIAN, TARGET_GNU_AS, TARGET_GNU_LD,
        TARGET_NO_PIC, TARGET_VOL_ASM_STOP, TARGET_ILP32, TARGET_REG_NAMES,
        TARGET_NO_SDATA, TARGET_CONST_GP, TARGET_AUTO_PIC,
        TARGET_INLINE_FLOAT_DIV_LAT, TARGET_INLINE_FLOAT_DIV_THR,
        TARGET_INLINE_INT_DIV_LAT, TARGET_INLINE_INT_DIV_THR,
        TARGET_INLINE_FLOAT_DIV, TARGET_INLINE_INT_DIV, TARGET_INLINE_SQRT_LAT,
        TARGET_INLINE_SQRT_THR, TARGET_INLINE_SQRT, TARGET_DWARF2_ASM,
        TARGET_EARLY_STOP_BITS): Remove.
        (TARGET_ILP32): Default false.
        (TARGET_SWITCHES, SUBTARGET_SWITCHES, TARGET_OPTIONS): Remove.
        (enum ia64_inline_type): New.
        (TARGET_DEFAULT): Remove MASK_INLINE_FLOAT_DIV_THR.
        * config/ia64/ia64.md: Update for new definitions of
        TARGET_INLINE_INT_DIV, TARGET_INLINE_FLOAT_DIV, TARGET_INLINE_SQRT.
        * config/ia64/ia64.opt: New file.
        * config/ia64/ilp32.opt: New file.

From-SVN: r96621
This commit is contained in:
Richard Henderson 2005-03-17 09:35:16 -08:00 committed by Richard Henderson
parent 0ee4e76d11
commit dbdd120f4c
8 changed files with 243 additions and 312 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
gcc/ChangeLog
View File

@ -1,3 +1,38 @@
2005-03-17 Richard Henderson <rth@redhat.com>
* config.gcc (ia64*-*-hpux*): Add extra_options.
* config/ia64/hpux.h (SUBTARGET_SWITCHES): Remove.
(TARGET_DEFAULT): Remove MASK_INLINE_FLOAT_DIV_THR.
* config/ia64/ia64.c (ia64_fixed_range_string): Remove.
(ia64_tls_size_string, ia64_tune_string): Remove.
(ia64_tune): Init to PROCESSOR_ITANIUM2.
(TARGET_DEFAULT_TARGET_FLAGS): New.
(TARGET_HANDLE_OPTION): New.
(ia64_override_options): Move options parsing ...
(ia64_handle_option): ... here. New.
* config/ia64/ia64.h (target_flags, MASK_BIG_ENDIAN, MASK_GNU_AS,
MASK_GNU_LD, MASK_NO_PIC, MASK_VOL_ASM_STOP, MASK_ILP32,
MASK_REG_NAMES, MASK_NO_SDATA, MASK_CONST_GP, MASK_AUTO_PIC,
MASK_INLINE_FLOAT_DIV_LAT, MASK_INLINE_FLOAT_DIV_THR,
MASK_INLINE_INT_DIV_LAT, MASK_INLINE_INT_DIV_THR,
MASK_INLINE_SQRT_LAT, MASK_INLINE_SQRT_THR, MASK_DWARF2_ASM,
MASK_EARLY_STOP_BITS, TARGET_BIG_ENDIAN, TARGET_GNU_AS, TARGET_GNU_LD,
TARGET_NO_PIC, TARGET_VOL_ASM_STOP, TARGET_ILP32, TARGET_REG_NAMES,
TARGET_NO_SDATA, TARGET_CONST_GP, TARGET_AUTO_PIC,
TARGET_INLINE_FLOAT_DIV_LAT, TARGET_INLINE_FLOAT_DIV_THR,
TARGET_INLINE_INT_DIV_LAT, TARGET_INLINE_INT_DIV_THR,
TARGET_INLINE_FLOAT_DIV, TARGET_INLINE_INT_DIV, TARGET_INLINE_SQRT_LAT,
TARGET_INLINE_SQRT_THR, TARGET_INLINE_SQRT, TARGET_DWARF2_ASM,
TARGET_EARLY_STOP_BITS): Remove.
(TARGET_ILP32): Default false.
(TARGET_SWITCHES, SUBTARGET_SWITCHES, TARGET_OPTIONS): Remove.
(enum ia64_inline_type): New.
(TARGET_DEFAULT): Remove MASK_INLINE_FLOAT_DIV_THR.
* config/ia64/ia64.md: Update for new definitions of
TARGET_INLINE_INT_DIV, TARGET_INLINE_FLOAT_DIV, TARGET_INLINE_SQRT.
* config/ia64/ia64.opt: New file.
* config/ia64/ilp32.opt: New file.
2005-03-17 H.J. Lu <hongjiu.lu@intel.com>
PR target/18380

1
gcc/config.gcc
View File

@ -1227,6 +1227,7 @@ ia64*-*-hpux*)
use_collect2=no
c_target_objs="ia64-c.o"
cxx_target_objs="ia64-c.o"
extra_options="${extra_options} ia64/ilp32.opt"
# If we decide to run fixproto we should define FIXPROTO_DEFINES
# in ia64/t-hpux, and also fix the definition of putenv in
# sys-protos.h (const char not char).

7
gcc/config/ia64/hpux.h
View File

@ -91,11 +91,6 @@ do { \
%{mlp64:-L/usr/lib/hpux64/libp} -lgprof} \
%{!symbolic:-lc}}"
#undef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES \
{ "ilp32", MASK_ILP32, "Generate ILP32 code" }, \
{ "lp64", -MASK_ILP32, "Generate LP64 code" },
#define MULTILIB_DEFAULTS { "milp32" }
/* A C expression whose value is zero if pointers that need to be extended
@ -109,7 +104,7 @@ do { \
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
(MASK_DWARF2_ASM | MASK_BIG_ENDIAN | MASK_ILP32 | MASK_INLINE_FLOAT_DIV_THR)
(MASK_DWARF2_ASM | MASK_BIG_ENDIAN | MASK_ILP32)
/* This needs to be set to force structure arguments with a single
integer field to be treated as structures and not as the type of

177
gcc/config/ia64/ia64.c
View File

@ -98,21 +98,12 @@ static const char * const ia64_local_reg_names[80] =
static const char * const ia64_output_reg_names[8] =
{ "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
/* String used with the -mfixed-range= option. */
const char *ia64_fixed_range_string;
/* Determines whether we use adds, addl, or movl to generate our
TLS immediate offsets. */
int ia64_tls_size = 22;
/* String used with the -mtls-size= option. */
const char *ia64_tls_size_string;
/* Which cpu are we scheduling for. */
enum processor_type ia64_tune;
/* String used with the -tune= option. */
const char *ia64_tune_string;
enum processor_type ia64_tune = PROCESSOR_ITANIUM2;
/* Determines whether we run our final scheduling pass or not. We always
avoid the normal second scheduling pass. */
@ -197,6 +188,7 @@ static bool ia64_function_ok_for_sibcall (tree, tree);
static bool ia64_return_in_memory (tree, tree);
static bool ia64_rtx_costs (rtx, int, int, int *);
static void fix_range (const char *);
static bool ia64_handle_option (size_t, const char *, int);
static struct machine_function * ia64_init_machine_status (void);
static void emit_insn_group_barriers (FILE *);
static void emit_all_insn_group_barriers (FILE *);
@ -433,6 +425,11 @@ static const struct attribute_spec ia64_attribute_table[] =
#undef TARGET_RELAXED_ORDERING
#define TARGET_RELAXED_ORDERING true
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
#undef TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION ia64_handle_option
struct gcc_target targetm = TARGET_INITIALIZER;
typedef enum
@ -4599,10 +4596,60 @@ fix_range (const char *const_str)
}
}
static struct machine_function *
ia64_init_machine_status (void)
/* Implement TARGET_HANDLE_OPTION. */
static bool
ia64_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
{
return ggc_alloc_cleared (sizeof (struct machine_function));
switch (code)
{
case OPT_mfixed_range_:
fix_range (arg);
return true;
case OPT_mtls_size_:
{
char *end;
unsigned long tmp = strtoul (arg, &end, 10);
if (*end || (tmp != 14 && tmp != 22 && tmp != 64))
error ("bad value %<%s%> for -mtls-size= switch", arg);
else
ia64_tls_size = tmp;
return true;
}
case OPT_mtune_:
{
static struct pta
{
const char *name; /* processor name or nickname. */
enum processor_type processor;
}
const processor_alias_table[] =
{
{"itanium", PROCESSOR_ITANIUM},
{"itanium1", PROCESSOR_ITANIUM},
{"merced", PROCESSOR_ITANIUM},
{"itanium2", PROCESSOR_ITANIUM2},
{"mckinley", PROCESSOR_ITANIUM2},
};
int const pta_size = ARRAY_SIZE (processor_alias_table);
int i;
for (i = 0; i < pta_size; i++)
if (!strcmp (arg, processor_alias_table[i].name))
{
ia64_tune = processor_alias_table[i].processor;
break;
}
if (i == pta_size)
error ("bad value %<%s%> for -mtune= switch", arg);
return true;
}
default:
return true;
}
}
/* Handle TARGET_OPTIONS switches. */
@ -4610,109 +4657,15 @@ ia64_init_machine_status (void)
void
ia64_override_options (void)
{
static struct pta
{
const char *const name; /* processor name or nickname. */
const enum processor_type processor;
}
const processor_alias_table[] =
{
{"itanium", PROCESSOR_ITANIUM},
{"itanium1", PROCESSOR_ITANIUM},
{"merced", PROCESSOR_ITANIUM},
{"itanium2", PROCESSOR_ITANIUM2},
{"mckinley", PROCESSOR_ITANIUM2},
};
int const pta_size = ARRAY_SIZE (processor_alias_table);
int i;
if (TARGET_AUTO_PIC)
target_flags |= MASK_CONST_GP;
if (TARGET_INLINE_FLOAT_DIV_LAT && TARGET_INLINE_FLOAT_DIV_THR)
{
if ((target_flags_explicit & MASK_INLINE_FLOAT_DIV_LAT)
&& (target_flags_explicit & MASK_INLINE_FLOAT_DIV_THR))
{
warning ("cannot optimize floating point division for both latency and throughput");
target_flags &= ~MASK_INLINE_FLOAT_DIV_THR;
}
else
{
if (target_flags_explicit & MASK_INLINE_FLOAT_DIV_THR)
target_flags &= ~MASK_INLINE_FLOAT_DIV_LAT;
else
target_flags &= ~MASK_INLINE_FLOAT_DIV_THR;
}
}
if (TARGET_INLINE_INT_DIV_LAT && TARGET_INLINE_INT_DIV_THR)
{
if ((target_flags_explicit & MASK_INLINE_INT_DIV_LAT)
&& (target_flags_explicit & MASK_INLINE_INT_DIV_THR))
{
warning ("cannot optimize integer division for both latency and throughput");
target_flags &= ~MASK_INLINE_INT_DIV_THR;
}
else
{
if (target_flags_explicit & MASK_INLINE_INT_DIV_THR)
target_flags &= ~MASK_INLINE_INT_DIV_LAT;
else
target_flags &= ~MASK_INLINE_INT_DIV_THR;
}
}
if (TARGET_INLINE_SQRT_LAT && TARGET_INLINE_SQRT_THR)
{
if ((target_flags_explicit & MASK_INLINE_SQRT_LAT)
&& (target_flags_explicit & MASK_INLINE_SQRT_THR))
{
warning ("cannot optimize square root for both latency and throughput");
target_flags &= ~MASK_INLINE_SQRT_THR;
}
else
{
if (target_flags_explicit & MASK_INLINE_SQRT_THR)
target_flags &= ~MASK_INLINE_SQRT_LAT;
else
target_flags &= ~MASK_INLINE_SQRT_THR;
}
}
if (TARGET_INLINE_SQRT_LAT)
if (TARGET_INLINE_SQRT == INL_MIN_LAT)
{
warning ("not yet implemented: latency-optimized inline square root");
target_flags &= ~MASK_INLINE_SQRT_LAT;
TARGET_INLINE_SQRT = INL_MAX_THR;
}
if (ia64_fixed_range_string)
fix_range (ia64_fixed_range_string);
if (ia64_tls_size_string)
{
char *end;
unsigned long tmp = strtoul (ia64_tls_size_string, &end, 10);
if (*end || (tmp != 14 && tmp != 22 && tmp != 64))
error ("bad value (%s) for -mtls-size= switch", ia64_tls_size_string);
else
ia64_tls_size = tmp;
}
if (!ia64_tune_string)
ia64_tune_string = "itanium2";
for (i = 0; i < pta_size; i++)
if (! strcmp (ia64_tune_string, processor_alias_table[i].name))
{
ia64_tune = processor_alias_table[i].processor;
break;
}
if (i == pta_size)
error ("bad value (%s) for -tune= switch", ia64_tune_string);
ia64_flag_schedule_insns2 = flag_schedule_insns_after_reload;
flag_schedule_insns_after_reload = 0;
@ -4725,6 +4678,12 @@ ia64_override_options (void)
init_machine_status = ia64_init_machine_status;
}
static struct machine_function *
ia64_init_machine_status (void)
{
return ggc_alloc_cleared (sizeof (struct machine_function));
}
static enum attr_itanium_class ia64_safe_itanium_class (rtx);
static enum attr_type ia64_safe_type (rtx);

192
gcc/config/ia64/ia64.h
View File

@ -27,8 +27,6 @@ Boston, MA 02111-1307, USA. */
/* ??? Functions containing a non-local goto target save many registers. Why?
See for instance execute/920428-2.c. */
/* ??? Add support for short data/bss sections. */
/* Run-time target specifications */
@ -56,92 +54,6 @@ do { \
#define ASM_EXTRA_SPEC ""
/* This declaration should be present. */
extern int target_flags;
/* This series of macros is to allow compiler command arguments to enable or
disable the use of optional features of the target machine. */
#define MASK_BIG_ENDIAN 0x00000001 /* Generate big endian code. */
#define MASK_GNU_AS 0x00000002 /* Generate code for GNU as. */
#define MASK_GNU_LD 0x00000004 /* Generate code for GNU ld. */
#define MASK_NO_PIC 0x00000008 /* Generate code without GP reg. */
#define MASK_VOL_ASM_STOP 0x00000010 /* Emit stop bits for vol ext asm. */
#define MASK_ILP32 0x00000020 /* Generate ILP32 code. */
#define MASK_REG_NAMES 0x00000080 /* Use in/loc/out register names. */
#define MASK_NO_SDATA 0x00000100 /* Disable sdata/scommon/sbss. */
#define MASK_CONST_GP 0x00000200 /* treat gp as program-wide constant */
#define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */
#define MASK_INLINE_FLOAT_DIV_LAT 0x00000800 /* inline div, min latency. */
#define MASK_INLINE_FLOAT_DIV_THR 0x00001000 /* inline div, max throughput. */
#define MASK_INLINE_INT_DIV_LAT 0x00002000 /* inline div, min latency. */
#define MASK_INLINE_INT_DIV_THR 0x00004000 /* inline div, max throughput. */
#define MASK_INLINE_SQRT_LAT 0x00008000 /* inline sqrt, min latency. */
#define MASK_INLINE_SQRT_THR 0x00010000 /* inline sqrt, max throughput. */
#define MASK_DWARF2_ASM 0x00020000 /* test dwarf2 line info via gas. */
#define MASK_EARLY_STOP_BITS 0x00040000 /* tune stop bits for the model. */
#define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
#define TARGET_GNU_AS (target_flags & MASK_GNU_AS)
#define TARGET_GNU_LD (target_flags & MASK_GNU_LD)
#define TARGET_NO_PIC (target_flags & MASK_NO_PIC)
#define TARGET_VOL_ASM_STOP (target_flags & MASK_VOL_ASM_STOP)
#define TARGET_ILP32 (target_flags & MASK_ILP32)
#define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES)
#define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA)
#define TARGET_CONST_GP (target_flags & MASK_CONST_GP)
#define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
#define TARGET_INLINE_FLOAT_DIV_LAT (target_flags & MASK_INLINE_FLOAT_DIV_LAT)
#define TARGET_INLINE_FLOAT_DIV_THR (target_flags & MASK_INLINE_FLOAT_DIV_THR)
#define TARGET_INLINE_INT_DIV_LAT (target_flags & MASK_INLINE_INT_DIV_LAT)
#define TARGET_INLINE_INT_DIV_THR (target_flags & MASK_INLINE_INT_DIV_THR)
#define TARGET_INLINE_FLOAT_DIV \
(target_flags & (MASK_INLINE_FLOAT_DIV_LAT | MASK_INLINE_FLOAT_DIV_THR))
#define TARGET_INLINE_INT_DIV \
(target_flags & (MASK_INLINE_INT_DIV_LAT | MASK_INLINE_INT_DIV_THR))
#define TARGET_INLINE_SQRT_LAT (target_flags & MASK_INLINE_SQRT_LAT)
#define TARGET_INLINE_SQRT_THR (target_flags & MASK_INLINE_SQRT_THR)
#define TARGET_INLINE_SQRT \
(target_flags & (MASK_INLINE_SQRT_LAT | MASK_INLINE_SQRT_THR))
#define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
/* Variables which are this size or smaller are put in the sdata/sbss
sections. */
extern unsigned int ia64_section_threshold;
@ -159,104 +71,40 @@ extern int ia64_tls_size;
#define TARGET_TLS14 (ia64_tls_size == 14)
#define TARGET_TLS22 (ia64_tls_size == 22)
#define TARGET_TLS64 (ia64_tls_size == 64)
#define TARGET_EARLY_STOP_BITS (target_flags & MASK_EARLY_STOP_BITS)
#define TARGET_HPUX 0
#define TARGET_HPUX_LD 0
#ifndef TARGET_ILP32
#define TARGET_ILP32 0
#endif
#ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS
#define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0
#endif
/* This macro defines names of command options to set and clear bits in
`target_flags'. Its definition is an initializer with a subgrouping for
each command option. */
/* Values for TARGET_INLINE_FLOAT_DIV, TARGET_INLINE_INT_DIV, and
TARGET_INLINE_SQRT. */
#define TARGET_SWITCHES \
{ \
{ "big-endian", MASK_BIG_ENDIAN, \
N_("Generate big endian code") }, \
{ "little-endian", -MASK_BIG_ENDIAN, \
N_("Generate little endian code") }, \
{ "gnu-as", MASK_GNU_AS, \
N_("Generate code for GNU as") }, \
{ "no-gnu-as", -MASK_GNU_AS, \
N_("Generate code for Intel as") }, \
{ "gnu-ld", MASK_GNU_LD, \
N_("Generate code for GNU ld") }, \
{ "no-gnu-ld", -MASK_GNU_LD, \
N_("Generate code for Intel ld") }, \
{ "no-pic", MASK_NO_PIC, \
N_("Generate code without GP reg") }, \
{ "volatile-asm-stop", MASK_VOL_ASM_STOP, \
N_("Emit stop bits before and after volatile extended asms") }, \
{ "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \
N_("Don't emit stop bits before and after volatile extended asms") }, \
{ "register-names", MASK_REG_NAMES, \
N_("Use in/loc/out register names")}, \
{ "no-sdata", MASK_NO_SDATA, \
N_("Disable use of sdata/scommon/sbss")}, \
{ "sdata", -MASK_NO_SDATA, \
N_("Enable use of sdata/scommon/sbss")}, \
{ "constant-gp", MASK_CONST_GP, \
N_("gp is constant (but save/restore gp on indirect calls)") }, \
{ "auto-pic", MASK_AUTO_PIC, \
N_("Generate self-relocatable code") }, \
{ "inline-float-divide-min-latency", MASK_INLINE_FLOAT_DIV_LAT, \
N_("Generate inline floating point division, optimize for latency") },\
{ "inline-float-divide-max-throughput", MASK_INLINE_FLOAT_DIV_THR, \
N_("Generate inline floating point division, optimize for throughput") },\
{ "no-inline-float-divide", \
-(MASK_INLINE_FLOAT_DIV_LAT|MASK_INLINE_FLOAT_DIV_THR), \
N_("Do not inline floating point division") }, \
{ "inline-int-divide-min-latency", MASK_INLINE_INT_DIV_LAT, \
N_("Generate inline integer division, optimize for latency") }, \
{ "inline-int-divide-max-throughput", MASK_INLINE_INT_DIV_THR, \
N_("Generate inline integer division, optimize for throughput") },\
{ "no-inline-int-divide", -(MASK_INLINE_INT_DIV_LAT|MASK_INLINE_INT_DIV_THR), \
N_("Do not inline integer division") }, \
{ "inline-sqrt-min-latency", MASK_INLINE_SQRT_LAT, \
N_("Generate inline square root, optimize for latency") }, \
{ "inline-sqrt-max-throughput", MASK_INLINE_SQRT_THR, \
N_("Generate inline square root, optimize for throughput") }, \
{ "no-inline-sqrt", -(MASK_INLINE_SQRT_LAT|MASK_INLINE_SQRT_THR), \
N_("Do not inline square root") }, \
{ "dwarf2-asm", MASK_DWARF2_ASM, \
N_("Enable Dwarf 2 line debug info via GNU as")}, \
{ "no-dwarf2-asm", -MASK_DWARF2_ASM, \
N_("Disable Dwarf 2 line debug info via GNU as")}, \
{ "early-stop-bits", MASK_EARLY_STOP_BITS, \
N_("Enable earlier placing stop bits for better scheduling")}, \
{ "no-early-stop-bits", -MASK_EARLY_STOP_BITS, \
N_("Disable earlier placing stop bits")}, \
SUBTARGET_SWITCHES \
{ "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
NULL } \
}
enum ia64_inline_type
{
INL_NO = 0,
INL_MIN_LAT = 1,
INL_MAX_THR = 2
};
/* Default target_flags if no switches are specified */
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_DWARF2_ASM | MASK_INLINE_FLOAT_DIV_THR)
#define TARGET_DEFAULT (MASK_DWARF2_ASM)
#endif
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT 0
#endif
#ifndef SUBTARGET_SWITCHES
#define SUBTARGET_SWITCHES
#endif
/* This macro is similar to `TARGET_SWITCHES' but defines names of command
options that have values. Its definition is an initializer with a
subgrouping for each command option. */
extern const char *ia64_fixed_range_string;
extern const char *ia64_tls_size_string;
/* Which processor to schedule for. The cpu attribute defines a list
that mirrors this list, so changes to i64.md must be made at the
that mirrors this list, so changes to ia64.md must be made at the
same time. */
enum processor_type
@ -268,18 +116,6 @@ enum processor_type
extern enum processor_type ia64_tune;
extern const char *ia64_tune_string;
#define TARGET_OPTIONS \
{ \
{ "fixed-range=", &ia64_fixed_range_string, \
N_("Specify range of registers to make fixed"), 0}, \
{ "tls-size=", &ia64_tls_size_string, \
N_("Specify bit size of immediate TLS offsets"), 0}, \
{ "tune=", &ia64_tune_string, \
N_("Schedule code for given CPU"), 0}, \
}
/* Sometimes certain combinations of command options do not make sense on a
particular target machine. You can define a macro `OVERRIDE_OPTIONS' to
take account of this. This macro, if defined, is executed once just after

38
gcc/config/ia64/ia64.md
View File

@ -2360,7 +2360,7 @@
op2_xf = gen_reg_rtx (XFmode);
expand_float (op2_xf, operands[2], 0);
if (TARGET_INLINE_INT_DIV_LAT)
if (TARGET_INLINE_INT_DIV == INL_MIN_LAT)
emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf));
else
emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf));
@ -2406,7 +2406,7 @@
op2_xf = gen_reg_rtx (XFmode);
expand_float (op2_xf, operands[2], 1);
if (TARGET_INLINE_INT_DIV_LAT)
if (TARGET_INLINE_INT_DIV == INL_MIN_LAT)
emit_insn (gen_divdi3_internal_lat (op0_xf, op1_xf, op2_xf));
else
emit_insn (gen_divdi3_internal_thr (op0_xf, op1_xf, op2_xf));
@ -2440,7 +2440,7 @@
(clobber (match_scratch:XF 4 "=&f"))
(clobber (match_scratch:XF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
"TARGET_INLINE_INT_DIV_LAT"
"TARGET_INLINE_INT_DIV == INL_MIN_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
@ -2499,7 +2499,7 @@
(clobber (match_scratch:XF 3 "=&f"))
(clobber (match_scratch:XF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
"TARGET_INLINE_INT_DIV_THR"
"TARGET_INLINE_INT_DIV == INL_MAX_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
@ -2678,7 +2678,7 @@
"TARGET_INLINE_FLOAT_DIV"
{
rtx insn;
if (TARGET_INLINE_FLOAT_DIV_LAT)
if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT)
insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]);
else
insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
@ -2693,7 +2693,7 @@
(clobber (match_scratch:XF 3 "=&f"))
(clobber (match_scratch:XF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
"TARGET_INLINE_FLOAT_DIV_LAT"
"TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
@ -2750,7 +2750,7 @@
(clobber (match_scratch:XF 3 "=&f"))
(clobber (match_scratch:XF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
"TARGET_INLINE_FLOAT_DIV_THR"
"TARGET_INLINE_FLOAT_DIV == INL_MAX_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
@ -2825,7 +2825,7 @@
"TARGET_INLINE_SQRT"
{
rtx insn;
if (TARGET_INLINE_SQRT_LAT)
if (TARGET_INLINE_SQRT == INL_MIN_LAT)
#if 0
insn = gen_sqrtsf2_internal_lat (operands[0], operands[1]);
#else
@ -2855,7 +2855,7 @@
(clobber (match_scratch:XF 5 "=&f"))
;; Register p6 in optimization guide.
(clobber (match_scratch:BI 6 "=c"))]
"TARGET_INLINE_SQRT_THR"
"TARGET_INLINE_SQRT == INL_MAX_THR"
"#"
"&& reload_completed"
[ ;; exponent of +1/2 in r2
@ -3160,7 +3160,7 @@
"TARGET_INLINE_FLOAT_DIV"
{
rtx insn;
if (TARGET_INLINE_FLOAT_DIV_LAT)
if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT)
insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]);
else
insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
@ -3176,7 +3176,7 @@
(clobber (match_scratch:XF 4 "=&f"))
(clobber (match_scratch:XF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))]
"TARGET_INLINE_FLOAT_DIV_LAT"
"TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9)))
@ -3256,7 +3256,7 @@
(clobber (match_scratch:XF 3 "=&f"))
(clobber (match_scratch:DF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
"TARGET_INLINE_FLOAT_DIV_THR"
"TARGET_INLINE_FLOAT_DIV == INL_MAX_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
@ -3323,7 +3323,7 @@
"TARGET_INLINE_SQRT"
{
rtx insn;
if (TARGET_INLINE_SQRT_LAT)
if (TARGET_INLINE_SQRT == INL_MIN_LAT)
#if 0
insn = gen_sqrtdf2_internal_lat (operands[0], operands[1]);
#else
@ -3353,7 +3353,7 @@
(clobber (match_scratch:XF 5 "=&f"))
;; Register p6 in optimization guide.
(clobber (match_scratch:BI 6 "=c"))]
"TARGET_INLINE_SQRT_THR"
"TARGET_INLINE_SQRT == INL_MAX_THR"
"#"
"&& reload_completed"
[ ;; exponent of +1/2 in r2
@ -3824,7 +3824,7 @@
"TARGET_INLINE_FLOAT_DIV"
{
rtx insn;
if (TARGET_INLINE_FLOAT_DIV_LAT)
if (TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT)
insn = gen_divxf3_internal_lat (operands[0], operands[1], operands[2]);
else
insn = gen_divxf3_internal_thr (operands[0], operands[1], operands[2]);
@ -3841,7 +3841,7 @@
(clobber (match_scratch:XF 5 "=&f"))
(clobber (match_scratch:XF 6 "=&f"))
(clobber (match_scratch:BI 7 "=c"))]
"TARGET_INLINE_FLOAT_DIV_LAT"
"TARGET_INLINE_FLOAT_DIV == INL_MIN_LAT"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
@ -3919,7 +3919,7 @@
(clobber (match_scratch:XF 3 "=&f"))
(clobber (match_scratch:XF 4 "=&f"))
(clobber (match_scratch:BI 5 "=c"))]
"TARGET_INLINE_FLOAT_DIV_THR"
"TARGET_INLINE_FLOAT_DIV == INL_MAX_THR"
"#"
"&& reload_completed"
[(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
@ -3998,7 +3998,7 @@
"TARGET_INLINE_SQRT"
{
rtx insn;
if (TARGET_INLINE_SQRT_LAT)
if (TARGET_INLINE_SQRT == INL_MIN_LAT)
#if 0
insn = gen_sqrtxf2_internal_lat (operands[0], operands[1]);
#else
@ -4030,7 +4030,7 @@
(clobber (match_scratch:XF 6 "=&f"))
;; Register p6 in optimization guide.
(clobber (match_scratch:BI 7 "=c"))]
"TARGET_INLINE_SQRT_THR"
"TARGET_INLINE_SQRT == INL_MAX_THR"
"#"
"&& reload_completed"
[ ;; exponent of +1/2 in r2

98
gcc/config/ia64/ia64.opt Normal file
View File

@ -0,0 +1,98 @@
mbig-endian
Target Report RejectNegative Mask(BIG_ENDIAN)
Generate big endian code
mlittle-endian
Target Report RejectNegative InverseMask(BIG_ENDIAN)
Generate little endian code
mgnu-as
Target Report Mask(GNU_AS)
Generate code for GNU as
mgnu-ld
Target Report Mask(GNU_LD)
Generate code for GNU ld
mvolatile-asm-stop
Target Report Mask(VOL_ASM_STOP)
Emit stop bits before and after volatile extended asms
mregister-names
Target Mask(REG_NAMES)
Use in/loc/out register names
mno-sdata
Target Report RejectNegative Mask(NO_SDATA)
msdata
Target Report RejectNegative InverseMask(NO_SDATA)
Enable use of sdata/scommon/sbss
mno-pic
Target Report RejectNegative Mask(NO_PIC)
Generate code without GP reg
mconstant-gp
Target Report RejectNegative Mask(CONST_GP)
gp is constant (but save/restore gp on indirect calls)
mauto-pic
Target Report RejectNegative Mask(AUTO_PIC)
Generate self-relocatable code
minline-float-divide-min-latency
Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 1)
Generate inline floating point division, optimize for latency
minline-float-divide-max-throughput
Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 2) Init(2)
Generate inline floating point division, optimize for throughput
mno-inline-float-divide
Target Report RejectNegative Var(TARGET_INLINE_FLOAT_DIV, 0)
minline-int-divide-min-latency
Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 1)
Generate inline integer division, optimize for latency
minline-int-divide-max-throughput
Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 2)
Generate inline integer division, optimize for throughput
mno-inline-int-divide
Target Report RejectNegative Var(TARGET_INLINE_INT_DIV, 0)
Do not inline integer division
minline-sqrt-min-latency
Target Report RejectNegative Var(TARGET_INLINE_SQRT, 1)
Generate inline square root, optimize for latency
minline-sqrt-max-throughput
Target Report RejectNegative Var(TARGET_INLINE_SQRT, 2)
Generate inline square root, optimize for throughput
mno-inline-sqrt
Target Report RejectNegative Var(TARGET_INLINE_SQRT, 0)
Do not inline square root
mdwarf2-asm
Target Report Mask(DWARF2_ASM)
Enable Dwarf 2 line debug info via GNU as
mearly-stop-bits
Target Report Mask(EARLY_STOP_BITS)
Enable earlier placing stop bits for better scheduling
mfixed-range=
Target RejectNegative Joined
Specify range of registers to make fixed
mtls-size=
Target RejectNegative Joined
Specify bit size of immediate TLS offsets
mtune=
Target RejectNegative Joined
Schedule code for given CPU

7
gcc/config/ia64/ilp32.opt Normal file
View File

@ -0,0 +1,7 @@
milp32
Target Report RejectNegative Mask(ILP32)
Generate ILP32 code
mlp64
Target Report RejectNegative InverseMask(ILP32)
Generate LP64 code