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boehm.c: Don't use bitmap as gc_descr if pointer is misaligned.
gcc/java/ 2007-09-06 Roman Zippel <zippel@linux-m68k.org> * boehm.c: Don't use bitmap as gc_descr if pointer is misaligned. libjava/ 2007-09-06 Roman Zippel <zippel@linux-m68k.org> * sysdep/m68k/locks.h: New file. * configure.host: Set sysdeps_dir and libgcj_interpreter for m68k. * configure.ac: Set SIGNAL_HANDLER for m68*-*-linux*. * configure: Regenerate. From-SVN: r128191
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@ -1,3 +1,7 @@
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2007-09-06 Roman Zippel <zippel@linux-m68k.org>
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* boehm.c: Don't use bitmap as gc_descr if pointer is misaligned.
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2007-09-06 Tom Tromey <tromey@redhat.com>
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* lang.c (java_post_options): Update.
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@ -97,6 +97,14 @@ mark_reference_fields (tree field,
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offset = int_byte_position (field);
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size_bytes = int_size_in_bytes (TREE_TYPE (field));
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if (offset % (POINTER_SIZE / BITS_PER_UNIT))
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{
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*all_bits_set = -1;
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*pointer_after_end = 1;
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break;
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}
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if (JREFERENCE_TYPE_P (TREE_TYPE (field))
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/* An `object' of type gnu.gcj.RawData is actually non-Java
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data. */
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@ -1,3 +1,10 @@
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2007-09-06 Roman Zippel <zippel@linux-m68k.org>
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* sysdep/m68k/locks.h: New file.
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* configure.host: Set sysdeps_dir and libgcj_interpreter for m68k.
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* configure.ac: Set SIGNAL_HANDLER for m68*-*-linux*.
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* configure: Regenerate.
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2007-09-05 Samuel Thibault <samuel.thibault@ens-lyon.org>
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* configure.host(gnu*): Set use_libgcj_bc to yes.
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3
libjava/configure
vendored
3
libjava/configure
vendored
@ -27265,6 +27265,9 @@ case "${host}" in
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mips*-*-linux*)
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SIGNAL_HANDLER=include/mips-signal.h
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;;
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m68*-*-linux*)
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SIGNAL_HANDLER=include/dwarf2-signal.h
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;;
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powerpc*-*-darwin*)
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SIGNAL_HANDLER=include/darwin-signal.h
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;;
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@ -1543,6 +1543,9 @@ case "${host}" in
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mips*-*-linux*)
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SIGNAL_HANDLER=include/mips-signal.h
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;;
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m68*-*-linux*)
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SIGNAL_HANDLER=include/dwarf2-signal.h
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;;
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powerpc*-*-darwin*)
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SIGNAL_HANDLER=include/darwin-signal.h
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;;
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@ -146,6 +146,10 @@ case "${host}" in
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libgcj_interpreter=yes
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enable_hash_synchronization_default=no
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;;
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m68k-*)
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sysdeps_dir=m68k
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libgcj_interpreter=yes
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;;
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powerpc64*-*)
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sysdeps_dir=powerpc
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libgcj_interpreter=yes
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@ -202,6 +206,7 @@ case "${host}" in
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ia64-* | \
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x86_64*-linux* | \
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hppa*-linux* | \
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m68k*-linux* | \
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sh-linux* | sh[34]*-linux*)
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can_unwind_signal=yes
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libgcj_ld_symbolic='-Wl,-Bsymbolic'
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72
libjava/sysdep/m68k/locks.h
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72
libjava/sysdep/m68k/locks.h
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// locks.h - Thread synchronization primitives. m68k implementation.
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/* Copyright (C) 2006 Free Software Foundation
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This file is part of libgcj.
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This software is copyrighted work licensed under the terms of the
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Libgcj License. Please consult the file "LIBGCJ_LICENSE" for
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details. */
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#ifndef __SYSDEP_LOCKS_H__
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#define __SYSDEP_LOCKS_H__
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/* Integer type big enough for object address. */
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typedef size_t obj_addr_t __attribute__ ((aligned (4)));
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// Atomically replace *addr by new_val if it was initially equal to old.
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// Return true if the comparison succeeded.
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// Assumed to have acquire semantics, i.e. later memory operations
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// cannot execute before the compare_and_swap finishes.
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static inline bool
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compare_and_swap(volatile obj_addr_t *addr,
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obj_addr_t old, obj_addr_t new_val)
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{
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char result;
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__asm__ __volatile__("cas.l %2,%3,%0; seq %1"
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: "+m" (*addr), "=d" (result), "+d" (old)
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: "d" (new_val)
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: "memory");
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return (bool) result;
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}
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// Set *addr to new_val with release semantics, i.e. making sure
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// that prior loads and stores complete before this
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// assignment.
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// On m68k, the hardware shouldn't reorder reads and writes,
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// so we just have to convince gcc not to do it either.
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static inline void
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release_set(volatile obj_addr_t *addr, obj_addr_t new_val)
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{
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__asm__ __volatile__(" " : : : "memory");
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*(addr) = new_val;
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}
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// Compare_and_swap with release semantics instead of acquire semantics.
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// On many architecture, the operation makes both guarantees, so the
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// implementation can be the same.
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static inline bool
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compare_and_swap_release(volatile obj_addr_t *addr,
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obj_addr_t old,
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obj_addr_t new_val)
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{
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return compare_and_swap(addr, old, new_val);
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}
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// Ensure that subsequent instructions do not execute on stale
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// data that was loaded from memory before the barrier.
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// On m68k, the hardware ensures that reads are properly ordered.
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static inline void
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read_barrier(void)
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{
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}
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// Ensure that prior stores to memory are completed with respect to other
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// processors.
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static inline void
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write_barrier(void)
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{
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// m68k does not reorder writes. We just need to ensure that gcc also doesn't.
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__asm__ __volatile__(" " : : : "memory");
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}
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#endif
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