diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8b8702a0a64d..7a6a3de89d91 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2004-12-15 Uros Bizjak + + * config/i386/i386.md (floathisf2, *floathisf2_1, floatsisf2, + *floatsisf2_i387, *floatsisf2_sse, floatdisf2, + *floatdisf2_i387_only, *floatdisf2_i387, *floatdisf2_sse, + floathidf2, *floathidf2_1, *floatsidf2_i387, *floatsidf2_sse, + floatdidf2, *floatdidf2_i387_only, *floatdidf2_i387, + *floatdidf2_sse, floatunssisf2, floatunsdisf2, floatunsdidf2): + Unify enable constraint with respect to TARGET_80387, TARGET_SSE, + TARGET_SSE2, TARGET_64BIT, TARGET_SSE_MATH and TARGET_MIX_SSE_I387. + (*float?i?f_i387): Rename to *float?i?f2_mixed. + (*float?i?f2_1): Rename to *float?i?f2_i387. + (*float?i?f2_i387_only): Rename to *float?i?f2_i387. + (float?ixf2): Penalize integer register operand. + 2004-12-14 John David Anglin PR c++/17242 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9b4b490fc91b..bf938be76c6e 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -4440,9 +4440,9 @@ (define_expand "floathisf2" [(set (match_operand:SF 0 "register_operand" "") (float:SF (match_operand:HI 1 "nonimmediate_operand" "")))] - "TARGET_SSE || TARGET_80387" + "TARGET_80387 || TARGET_SSE_MATH" { - if (TARGET_SSE && TARGET_SSE_MATH) + if (TARGET_SSE_MATH) { emit_insn (gen_floatsisf2 (operands[0], convert_to_mode (SImode, operands[1], 0))); @@ -4450,10 +4450,10 @@ } }) -(define_insn "*floathisf2_1" +(define_insn "*floathisf2_i387" [(set (match_operand:SF 0 "register_operand" "=f,f") - (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] - "TARGET_80387 && (!TARGET_SSE || !TARGET_SSE_MATH)" + (float:SF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))] + "TARGET_80387 && !TARGET_SSE_MATH" "@ fild%z1\t%1 #" @@ -4464,13 +4464,13 @@ (define_expand "floatsisf2" [(set (match_operand:SF 0 "register_operand" "") (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] - "TARGET_SSE || TARGET_80387" + "TARGET_80387 || TARGET_SSE_MATH" "") -(define_insn "*floatsisf2_i387" +(define_insn "*floatsisf2_mixed" [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f") (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))] - "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)" + "TARGET_MIX_SSE_I387" "@ fild%z1\t%1 # @@ -4484,7 +4484,7 @@ (define_insn "*floatsisf2_sse" [(set (match_operand:SF 0 "register_operand" "=x,x") (float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))] - "TARGET_SSE" + "TARGET_SSE_MATH" "cvtsi2ss\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "mode" "SF") @@ -4496,7 +4496,8 @@ (define_split [(set (match_operand:SF 0 "register_operand" "") (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] - "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS + "reload_completed + && TARGET_SSE_MATH && TARGET_SSE_PARTIAL_REGS && SSE_REG_P (operands[0])" [(const_int 0)] { @@ -4507,16 +4508,10 @@ DONE; }) -(define_expand "floatdisf2" - [(set (match_operand:SF 0 "register_operand" "") - (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))] - "(TARGET_64BIT && TARGET_SSE) || TARGET_80387" - "") - -(define_insn "*floatdisf2_i387_only" - [(set (match_operand:SF 0 "register_operand" "=f,?f") - (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] - "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)" +(define_insn "*floatsisf2_i387" + [(set (match_operand:SF 0 "register_operand" "=f,f") + (float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))] + "TARGET_80387" "@ fild%z1\t%1 #" @@ -4524,10 +4519,16 @@ (set_attr "mode" "SF") (set_attr "fp_int_src" "true")]) -(define_insn "*floatdisf2_i387" +(define_expand "floatdisf2" + [(set (match_operand:SF 0 "register_operand" "") + (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))] + "TARGET_80387 || (TARGET_64BIT && TARGET_SSE_MATH)" + "") + +(define_insn "*floatdisf2_mixed" [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f") (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))] - "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)" + "TARGET_64BIT && TARGET_MIX_SSE_I387" "@ fild%z1\t%1 # @@ -4541,7 +4542,7 @@ (define_insn "*floatdisf2_sse" [(set (match_operand:SF 0 "register_operand" "=x,x") (float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))] - "TARGET_64BIT && TARGET_SSE" + "TARGET_64BIT && TARGET_SSE_MATH" "cvtsi2ss{q}\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "mode" "SF") @@ -4553,7 +4554,8 @@ (define_split [(set (match_operand:SF 0 "register_operand" "") (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))] - "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS + "reload_completed + && TARGET_64BIT && TARGET_SSE_MATH && TARGET_SSE_PARTIAL_REGS && SSE_REG_P (operands[0])" [(const_int 0)] { @@ -4564,12 +4566,23 @@ DONE; }) +(define_insn "*floatdisf2_i387" + [(set (match_operand:SF 0 "register_operand" "=f,f") + (float:SF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))] + "TARGET_80387" + "@ + fild%z1\t%1 + #" + [(set_attr "type" "fmov,multi") + (set_attr "mode" "SF") + (set_attr "fp_int_src" "true")]) + (define_expand "floathidf2" [(set (match_operand:DF 0 "register_operand" "") (float:DF (match_operand:HI 1 "nonimmediate_operand" "")))] - "TARGET_SSE2 || TARGET_80387" + "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" { - if (TARGET_SSE && TARGET_SSE_MATH) + if (TARGET_SSE2 && TARGET_SSE_MATH) { emit_insn (gen_floatsidf2 (operands[0], convert_to_mode (SImode, operands[1], 0))); @@ -4577,10 +4590,10 @@ } }) -(define_insn "*floathidf2_1" +(define_insn "*floathidf2_i387" [(set (match_operand:DF 0 "register_operand" "=f,f") - (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] - "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)" + (float:DF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))] + "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)" "@ fild%z1\t%1 #" @@ -4591,13 +4604,13 @@ (define_expand "floatsidf2" [(set (match_operand:DF 0 "register_operand" "") (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))] - "TARGET_80387 || TARGET_SSE2" + "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" "") -(define_insn "*floatsidf2_i387" +(define_insn "*floatsidf2_mixed" [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f") (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))] - "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)" + "TARGET_SSE2 && TARGET_MIX_SSE_I387" "@ fild%z1\t%1 # @@ -4611,23 +4624,17 @@ (define_insn "*floatsidf2_sse" [(set (match_operand:DF 0 "register_operand" "=Y,Y") (float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))] - "TARGET_SSE2" + "TARGET_SSE2 && TARGET_SSE_MATH" "cvtsi2sd\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "mode" "DF") (set_attr "athlon_decode" "double,direct") (set_attr "fp_int_src" "true")]) -(define_expand "floatdidf2" - [(set (match_operand:DF 0 "register_operand" "") - (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))] - "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387" - "") - -(define_insn "*floatdidf2_i387_only" - [(set (match_operand:DF 0 "register_operand" "=f,?f") - (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] - "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)" +(define_insn "*floatsidf2_i387" + [(set (match_operand:DF 0 "register_operand" "=f,f") + (float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))] + "TARGET_80387" "@ fild%z1\t%1 #" @@ -4635,10 +4642,16 @@ (set_attr "mode" "DF") (set_attr "fp_int_src" "true")]) -(define_insn "*floatdidf2_i387" +(define_expand "floatdidf2" + [(set (match_operand:DF 0 "register_operand" "") + (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))] + "TARGET_80387 || (TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH)" + "") + +(define_insn "*floatdidf2_mixed" [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f") (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))] - "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)" + "TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387" "@ fild%z1\t%1 # @@ -4652,16 +4665,27 @@ (define_insn "*floatdidf2_sse" [(set (match_operand:DF 0 "register_operand" "=Y,Y") (float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))] - "TARGET_SSE2" + "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH" "cvtsi2sd{q}\t{%1, %0|%0, %1}" [(set_attr "type" "sseicvt") (set_attr "mode" "DF") (set_attr "athlon_decode" "double,direct") (set_attr "fp_int_src" "true")]) +(define_insn "*floatdidf2_i387" + [(set (match_operand:DF 0 "register_operand" "=f,f") + (float:DF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))] + "TARGET_80387" + "@ + fild%z1\t%1 + #" + [(set_attr "type" "fmov,multi") + (set_attr "mode" "DF") + (set_attr "fp_int_src" "true")]) + (define_insn "floathixf2" [(set (match_operand:XF 0 "register_operand" "=f,f") - (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))] + (float:XF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))] "TARGET_80387" "@ fild%z1\t%1 @@ -4672,7 +4696,7 @@ (define_insn "floatsixf2" [(set (match_operand:XF 0 "register_operand" "=f,f") - (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))] + (float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))] "TARGET_80387" "@ fild%z1\t%1 @@ -4683,7 +4707,7 @@ (define_insn "floatdixf2" [(set (match_operand:XF 0 "register_operand" "=f,f") - (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))] + (float:XF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))] "TARGET_80387" "@ fild%z1\t%1 @@ -4696,7 +4720,9 @@ (define_split [(set (match_operand 0 "fp_register_operand" "") (float (match_operand 1 "register_operand" "")))] - "reload_completed && FLOAT_MODE_P (GET_MODE (operands[0]))" + "reload_completed + && TARGET_80387 + && FLOAT_MODE_P (GET_MODE (operands[0]))" [(const_int 0)] { operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]); @@ -4709,19 +4735,19 @@ (define_expand "floatunssisf2" [(use (match_operand:SF 0 "register_operand" "")) (use (match_operand:SI 1 "register_operand" ""))] - "TARGET_SSE && TARGET_SSE_MATH && !TARGET_64BIT" + "!TARGET_64BIT && TARGET_SSE_MATH" "x86_emit_floatuns (operands); DONE;") (define_expand "floatunsdisf2" [(use (match_operand:SF 0 "register_operand" "")) (use (match_operand:DI 1 "register_operand" ""))] - "TARGET_SSE && TARGET_SSE_MATH && TARGET_64BIT" + "TARGET_64BIT && TARGET_SSE_MATH" "x86_emit_floatuns (operands); DONE;") (define_expand "floatunsdidf2" [(use (match_operand:DF 0 "register_operand" "")) (use (match_operand:DI 1 "register_operand" ""))] - "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_64BIT" + "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH" "x86_emit_floatuns (operands); DONE;") ;; SSE extract/set expanders