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i386.c (ix86_expand_builtin): If gather mask argument is known to have all high bits set...
* config/i386/i386.c (ix86_expand_builtin): If gather mask argument is known to have all high bits set, pass pc_rtx as second argument to the expander instead of op0. * config/i386/sse.md (*avx2_gathersi<mode>_2, *avx2_gatherdi<mode>_2): New patterns. * config/i386/avx2intrin.h (_mm256_i32gather_pd, _mm256_i64gather_pd, _mm256_i32gather_ps): Set mask using _mm256_cmp_pd with zero vector arguments and _CMP_EQ_OQ instead of _mm256_set1_pd. From-SVN: r181090
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Jakub Jelinek
Jakub Jelinek
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gcc
@ -1,5 +1,15 @@
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2011-11-07 Jakub Jelinek <jakub@redhat.com>
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* config/i386/i386.c (ix86_expand_builtin): If gather mask
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argument is known to have all high bits set, pass pc_rtx as
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second argument to the expander instead of op0.
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* config/i386/sse.md (*avx2_gathersi<mode>_2,
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*avx2_gatherdi<mode>_2): New patterns.
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* config/i386/avx2intrin.h (_mm256_i32gather_pd,
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_mm256_i64gather_pd, _mm256_i32gather_ps): Set mask using
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_mm256_cmp_pd with zero vector arguments and _CMP_EQ_OQ instead of
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_mm256_set1_pd.
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PR tree-optimization/50789
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* tree-vect-stmts.c (process_use): Add force argument, avoid
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exist_non_indexing_operands_for_use_p check if true.
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@ -1252,7 +1252,7 @@ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_i32gather_pd (double const *base, __m128i index, const int scale)
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{
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__v4df src = _mm256_setzero_pd ();
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__v4df mask = _mm256_set1_pd((double)(long long int) -1);
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__v4df mask = _mm256_cmp_pd (src, src, _CMP_EQ_OQ);
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return (__m256d) __builtin_ia32_gathersiv4df (src,
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base,
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@ -1304,7 +1304,7 @@ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_i64gather_pd (double const *base, __m256i index, const int scale)
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{
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__v4df src = _mm256_setzero_pd ();
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__v4df mask = _mm256_set1_pd((double)(long long int) -1);
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__v4df mask = _mm256_cmp_pd (src, src, _CMP_EQ_OQ);
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return (__m256d) __builtin_ia32_gatherdiv4df (src,
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base,
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@ -1356,7 +1356,7 @@ __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
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_mm256_i32gather_ps (float const *base, __m256i index, const int scale)
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{
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__v8sf src = _mm256_setzero_ps ();
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__v8sf mask = _mm256_set1_ps((float)(int) -1);
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__v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
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return (__m256) __builtin_ia32_gathersiv8sf (src,
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base,
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@ -29087,6 +29087,71 @@ rdrand_step:
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error ("last argument must be scale 1, 2, 4, 8");
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return const0_rtx;
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}
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/* Optimize. If mask is known to have all high bits set,
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replace op0 with pc_rtx to signal that the instruction
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overwrites the whole destination and doesn't use its
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previous contents. */
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if (optimize)
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{
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if (TREE_CODE (arg3) == VECTOR_CST)
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{
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tree elt;
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unsigned int negative = 0;
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for (elt = TREE_VECTOR_CST_ELTS (arg3);
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elt; elt = TREE_CHAIN (elt))
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{
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tree cst = TREE_VALUE (elt);
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if (TREE_CODE (cst) == INTEGER_CST
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&& tree_int_cst_sign_bit (cst))
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negative++;
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else if (TREE_CODE (cst) == REAL_CST
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&& REAL_VALUE_NEGATIVE (TREE_REAL_CST (cst)))
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negative++;
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}
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if (negative == TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg3)))
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op0 = pc_rtx;
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}
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else if (TREE_CODE (arg3) == SSA_NAME)
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{
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/* Recognize also when mask is like:
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__v2df src = _mm_setzero_pd ();
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__v2df mask = _mm_cmpeq_pd (src, src);
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or
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__v8sf src = _mm256_setzero_ps ();
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__v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
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as that is a cheaper way to load all ones into
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a register than having to load a constant from
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memory. */
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gimple def_stmt = SSA_NAME_DEF_STMT (arg3);
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if (is_gimple_call (def_stmt))
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{
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tree fndecl = gimple_call_fndecl (def_stmt);
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if (fndecl
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&& DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD)
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switch ((unsigned int) DECL_FUNCTION_CODE (fndecl))
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{
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case IX86_BUILTIN_CMPPD:
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case IX86_BUILTIN_CMPPS:
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case IX86_BUILTIN_CMPPD256:
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case IX86_BUILTIN_CMPPS256:
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if (!integer_zerop (gimple_call_arg (def_stmt, 2)))
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break;
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/* FALLTHRU */
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case IX86_BUILTIN_CMPEQPD:
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case IX86_BUILTIN_CMPEQPS:
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if (initializer_zerop (gimple_call_arg (def_stmt, 0))
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&& initializer_zerop (gimple_call_arg (def_stmt,
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1)))
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op0 = pc_rtx;
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break;
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default:
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break;
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}
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}
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}
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}
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pat = GEN_FCN (icode) (subtarget, op0, op1, op2, op3, op4);
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if (! pat)
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return const0_rtx;
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@ -12567,6 +12567,26 @@
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(set_attr "prefix" "vex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "*avx2_gathersi<mode>_2"
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[(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x")
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(unspec:VEC_GATHER_MODE
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[(pc)
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(match_operator:<ssescalarmode> 6 "vsib_mem_operator"
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[(unspec:P
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[(match_operand:P 2 "vsib_address_operand" "p")
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(match_operand:<VEC_GATHER_IDXSI> 3 "register_operand" "x")
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(match_operand:SI 5 "const1248_operand" "n")]
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UNSPEC_VSIBADDR)])
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(mem:BLK (scratch))
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(match_operand:VEC_GATHER_MODE 4 "register_operand" "1")]
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UNSPEC_GATHER))
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(clobber (match_scratch:VEC_GATHER_MODE 1 "=&x"))]
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"TARGET_AVX2"
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"v<sseintprefix>gatherd<ssemodesuffix>\t{%1, %6, %0|%0, %6, %1}"
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[(set_attr "type" "ssemov")
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(set_attr "prefix" "vex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_expand "avx2_gatherdi<mode>"
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[(parallel [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "")
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(unspec:VEC_GATHER_MODE
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@ -12608,3 +12628,27 @@
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[(set_attr "type" "ssemov")
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(set_attr "prefix" "vex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "*avx2_gatherdi<mode>_2"
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[(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x")
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(unspec:VEC_GATHER_MODE
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[(pc)
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(match_operator:<ssescalarmode> 6 "vsib_mem_operator"
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[(unspec:P
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[(match_operand:P 2 "vsib_address_operand" "p")
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(match_operand:<VEC_GATHER_IDXDI> 3 "register_operand" "x")
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(match_operand:SI 5 "const1248_operand" "n")]
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UNSPEC_VSIBADDR)])
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(mem:BLK (scratch))
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(match_operand:<VEC_GATHER_SRCDI> 4 "register_operand" "1")]
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UNSPEC_GATHER))
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(clobber (match_scratch:VEC_GATHER_MODE 1 "=&x"))]
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"TARGET_AVX2"
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{
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if (<MODE>mode != <VEC_GATHER_SRCDI>mode)
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return "v<sseintprefix>gatherq<ssemodesuffix>\t{%4, %6, %x0|%x0, %6, %4}";
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return "v<sseintprefix>gatherq<ssemodesuffix>\t{%4, %6, %0|%0, %6, %4}";
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}
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[(set_attr "type" "ssemov")
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(set_attr "prefix" "vex")
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(set_attr "mode" "<sseinsnmode>")])
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