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Remove *mmx_maskmovq_rex.

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2011-10-25  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/mmx.md (*mmx_maskmovq): Replace :SI with :P and
	remove "&& !TARGET_64BIT"
	(*mmx_maskmovq_rex): Removed.

From-SVN: r180458
This commit is contained in:
H.J. Lu 2011-10-25 22:54:48 +00:00 committed by H.J. Lu
parent 95d17cbf6d
commit d7115452b2
2 changed files with 8 additions and 14 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2011-10-25 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/mmx.md (*mmx_maskmovq): Replace :SI with :P and
remove "&& !TARGET_64BIT"
(*mmx_maskmovq_rex): Removed.
2011-10-25 Eric Botcazou <ebotcazou@adacore.com>
PR rtl-optimization/46603

16
gcc/config/i386/mmx.md
View File

@ -1656,24 +1656,12 @@
"TARGET_SSE || TARGET_3DNOW_A")
(define_insn "*mmx_maskmovq"
[(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
[(set (mem:V8QI (match_operand:P 0 "register_operand" "D"))
(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
(match_operand:V8QI 2 "register_operand" "y")
(mem:V8QI (match_dup 0))]
UNSPEC_MASKMOV))]
"(TARGET_SSE || TARGET_3DNOW_A) && !TARGET_64BIT"
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovq\t{%2, %1|%1, %2}"
[(set_attr "type" "mmxcvt")
(set_attr "mode" "DI")])
(define_insn "*mmx_maskmovq_rex"
[(set (mem:V8QI (match_operand:DI 0 "register_operand" "D"))
(unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y")
(match_operand:V8QI 2 "register_operand" "y")
(mem:V8QI (match_dup 0))]
UNSPEC_MASKMOV))]
"(TARGET_SSE || TARGET_3DNOW_A) && TARGET_64BIT"
"TARGET_SSE || TARGET_3DNOW_A"
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovq\t{%2, %1|%1, %2}"
[(set_attr "type" "mmxcvt")