diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f323db25c7b..0f48a0d4eaa 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2003-08-19  Chris Demetriou  <cgd@broadcom.com>
+
+	* config/mips/mips.md: Adjust SI-mode "trap_if" instruction
+	to use better predicates and constraints.  Define new
+	instruction to handle "trap_if" with DI-mode arguments.
+	(conditional_trap): FAIL if trap code is not 0.
+
 2003-08-19  Andrew Pinski  <pinskia@physics.uc.edu>
 
 	* config/i386/i386.c (legitimate_pic_address_disp_p): Change the
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 6e6deb8fcba..832140e409e 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -640,17 +640,30 @@
 	    (match_operand 1 "const_int_operand" ""))]
   "ISA_HAS_COND_TRAP"
 {
-  mips_gen_conditional_trap (operands);
-  DONE;
+  if (operands[1] == const0_rtx)
+    {
+      mips_gen_conditional_trap (operands);
+      DONE;
+    }
+  else
+    FAIL;
 })
 
 (define_insn ""
   [(trap_if (match_operator 0 "trap_cmp_op"
-                            [(match_operand:SI 1 "reg_or_0_operand" "d")
-                             (match_operand:SI 2 "nonmemory_operand" "dI")])
+                            [(match_operand:SI 1 "reg_or_0_operand" "dJ")
+                             (match_operand:SI 2 "arith_operand" "dI")])
 	    (const_int 0))]
   "ISA_HAS_COND_TRAP"
   "t%C0\t%z1,%z2")
+
+(define_insn ""
+  [(trap_if (match_operator 0 "trap_cmp_op"
+                            [(match_operand:DI 1 "reg_or_0_operand" "dJ")
+                             (match_operand:DI 2 "arith_operand" "dI")])
+	    (const_int 0))]
+  "TARGET_64BIT && ISA_HAS_COND_TRAP"
+  "t%C0\t%z1,%z2")
 
 ;;
 ;;  ....................