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arm: Add vst1_lane_bf16 + vstq_lane_bf16 intrinsics

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gcc/ChangeLog

2020-10-23  Andrea Corallo  <andrea.corallo@arm.com>

	* config/arm/arm_neon.h (vst1_lane_bf16, vst1q_lane_bf16): Add
	intrinsics.
	* config/arm/arm_neon_builtins.def (STORE1LANE): Add v4bf, v8bf.

gcc/testsuite/ChangeLog

2020-10-23  Andrea Corallo  <andrea.corallo@arm.com>

	* gcc.target/arm/simd/vst1_lane_bf16_1.c: New testcase.
	* gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c: Likewise.
	* gcc.target/arm/simd/vst1_lane_bf16_indices_1.c: Likewise.
This commit is contained in:
Andrea Corallo 2020-10-23 14:21:56 +02:00
parent c9a0276840
commit d65303b699
5 changed files with 67 additions and 2 deletions
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14
gcc/config/arm/arm_neon.h
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@ -19679,6 +19679,20 @@ vld1q_lane_bf16 (const bfloat16_t * __a, bfloat16x8_t __b, const int __c)
return __builtin_neon_vld1_lanev8bf (__a, __b, __c);
}
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1_lane_bf16 (bfloat16_t * __a, bfloat16x4_t __b, const int __c)
{
__builtin_neon_vst1_lanev4bf (__a, __b, __c);
}
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1q_lane_bf16 (bfloat16_t * __a, bfloat16x8_t __b, const int __c)
{
__builtin_neon_vst1_lanev8bf (__a, __b, __c);
}
#pragma GCC pop_options
#ifdef __cplusplus

4
gcc/config/arm/arm_neon_builtins.def
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@ -318,8 +318,8 @@ VAR10 (LOAD1, vld1_dup,
v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
VAR12 (STORE1, vst1,
v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di)
VAR12 (STORE1LANE, vst1_lane,
v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di)
VAR14 (STORE1LANE, vst1_lane,
v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf)
VAR13 (LOAD1, vld2,
v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v4bf, v8bf)
VAR9 (LOAD1LANE, vld2_lane,

21
gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c Normal file
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@ -0,0 +1,21 @@
/* { dg-do assemble } */
/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
/* { dg-add-options arm_v8_2a_bf16_neon } */
/* { dg-additional-options "-O3 --save-temps" } */
#include "arm_neon.h"
void
test_vst1_lane_bf16 (bfloat16_t *a, bfloat16x4_t b)
{
vst1_lane_bf16 (a, b, 1);
}
void
test_vst1q_lane_bf16 (bfloat16_t *a, bfloat16x8_t b)
{
vst1q_lane_bf16 (a, b, 2);
}
/* { dg-final { scan-assembler "vst1.16\t{d0\\\[1\\\]}, \\\[r0\\\]" } } */
/* { dg-final { scan-assembler "vst1.16\t{d0\\\[2\\\]}, \\\[r0\\\]" } } */

15
gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c Normal file
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@ -0,0 +1,15 @@
/* { dg-do assemble } */
/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
/* { dg-add-options arm_v8_2a_bf16_neon } */
#include "arm_neon.h"
void
test_vst1_lane_bf16 (bfloat16_t *a, bfloat16x4_t b)
{
vst1_lane_bf16 (a, b, -1);
vst1_lane_bf16 (a, b, 4);
}
/* { dg-error "lane -1 out of range 0 - 3" "" { target *-*-* } 0 } */
/* { dg-error "lane 4 out of range 0 - 3" "" { target *-*-* } 0 } */

15
gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c Normal file
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@ -0,0 +1,15 @@
/* { dg-do assemble } */
/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
/* { dg-add-options arm_v8_2a_bf16_neon } */
#include "arm_neon.h"
void
test_vstq1_lane_bf16 (bfloat16_t *a, bfloat16x8_t b)
{
vst1q_lane_bf16 (a, b, -1);
vst1q_lane_bf16 (a, b, 8);
}
/* { dg-error "lane -1 out of range 0 - 7" "" { target *-*-* } 0 } */
/* { dg-error "lane 8 out of range 0 - 7" "" { target *-*-* } 0 } */