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aarch64: Fix +nosimd handling of FPR moves
8-bit and 16-bit FPR moves would ICE for +nosimd+fp, and some other moves would handle FPR<-zero inefficiently. This is very much a niche case at the moment, but something like it becomes more important with SME streaming mode. The si, di and vector tests already passed, they're just included for completeness. We're a bit inconsistent about whether alternatives involving FPRs are marked with arch==fp or arch=* (i.e. default). E.g. FPR loads and stores are sometimes * and sometimes fp. IMO * makes more sense. FPRs should not be used at all without TARGET_FLOAT, so TARGET_FLOAT represents the base architecture when FPRs are enabled. I think it's more useful if non-default arches represent a genuine restriction. gcc/ * config/aarch64/aarch64.md (*mov<SHORT:mode>_aarch64): Extend w<-w, r<-w and w<-r alternatives to !simd, using 32-bit moves in that case. Extend w<-r to w<-Z. (*mov<HFBF:mode>_aarch64): Likewise, but with Y instead of Z. (*movti_aarch64): Use an FMOV from XZR for w<-Z if MOVI is not available. (define_split): Do not apply the floating-point immediate-to-register split to zeros, even if MOVI is not available. gcc/testsuite/ * gcc.target/aarch64/movqi_1.c: New test. * gcc.target/aarch64/movhi_1.c: Likewise. * gcc.target/aarch64/movsi_1.c: Likewise. * gcc.target/aarch64/movdi_2.c: Likewise. * gcc.target/aarch64/movti_2.c: Likewise. * gcc.target/aarch64/movhf_1.c: Likewise. * gcc.target/aarch64/movsf_1.c: Likewise. * gcc.target/aarch64/movdf_1.c: Likewise. * gcc.target/aarch64/movtf_2.c: Likewise. * gcc.target/aarch64/movv8qi_1.c: Likewise. * gcc.target/aarch64/movv16qi_1.c: Likewise.
This commit is contained in:
Richard Sandiford
parent
f58d5545d6
commit
d610613290
@ -1195,7 +1195,7 @@
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(define_insn "*mov<mode>_aarch64"
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[(set (match_operand:SHORT 0 "nonimmediate_operand" "=r,r, w,r ,r,w, m,m,r,w,w")
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(match_operand:SHORT 1 "aarch64_mov_operand" " r,M,D<hq>,Usv,m,m,rZ,w,w,r,w"))]
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(match_operand:SHORT 1 "aarch64_mov_operand" " r,M,D<hq>,Usv,m,m,rZ,w,w,rZ,w"))]
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"(register_operand (operands[0], <MODE>mode)
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|| aarch64_reg_or_zero (operands[1], <MODE>mode))"
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{
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@ -1219,11 +1219,11 @@
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case 7:
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return "str\t%<size>1, %0";
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case 8:
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return "umov\t%w0, %1.<v>[0]";
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return TARGET_SIMD ? "umov\t%w0, %1.<v>[0]" : "fmov\t%w0, %s1";
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case 9:
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return "dup\t%0.<Vallxd>, %w1";
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return TARGET_SIMD ? "dup\t%0.<Vallxd>, %w1" : "fmov\t%s0, %w1";
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case 10:
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return "dup\t%<Vetype>0, %1.<v>[0]";
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return TARGET_SIMD ? "dup\t%<Vetype>0, %1.<v>[0]" : "fmov\t%s0, %s1";
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default:
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gcc_unreachable ();
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}
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@ -1231,7 +1231,7 @@
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;; The "mov_imm" type for CNT is just a placeholder.
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[(set_attr "type" "mov_reg,mov_imm,neon_move,mov_imm,load_4,load_4,store_4,
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store_4,neon_to_gp<q>,neon_from_gp<q>,neon_dup")
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(set_attr "arch" "*,*,simd,sve,*,*,*,*,simd,simd,simd")]
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(set_attr "arch" "*,*,simd,sve,*,*,*,*,*,*,*")]
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)
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(define_expand "mov<mode>"
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@ -1393,14 +1393,15 @@
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(define_insn "*movti_aarch64"
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[(set (match_operand:TI 0
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"nonimmediate_operand" "= r,w,w, r,w,r,m,m,w,m")
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"nonimmediate_operand" "= r,w,w,w, r,w,r,m,m,w,m")
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(match_operand:TI 1
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"aarch64_movti_operand" " rUti,Z,r, w,w,m,r,Z,m,w"))]
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"aarch64_movti_operand" " rUti,Z,Z,r, w,w,m,r,Z,m,w"))]
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"(register_operand (operands[0], TImode)
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|| aarch64_reg_or_zero (operands[1], TImode))"
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"@
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#
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movi\\t%0.2d, #0
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fmov\t%d0, xzr
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#
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#
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mov\\t%0.16b, %1.16b
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@ -1409,11 +1410,11 @@
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stp\\txzr, xzr, %0
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ldr\\t%q0, %1
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str\\t%q1, %0"
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[(set_attr "type" "multiple,neon_move,f_mcr,f_mrc,neon_logic_q, \
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[(set_attr "type" "multiple,neon_move,f_mcr,f_mcr,f_mrc,neon_logic_q, \
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load_16,store_16,store_16,\
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load_16,store_16")
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(set_attr "length" "8,4,8,8,4,4,4,4,4,4")
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(set_attr "arch" "*,simd,*,*,simd,*,*,*,fp,fp")]
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(set_attr "length" "8,4,4,8,8,4,4,4,4,4,4")
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(set_attr "arch" "*,simd,*,*,*,simd,*,*,*,fp,fp")]
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)
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;; Split a TImode register-register or register-immediate move into
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@ -1452,16 +1453,19 @@
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)
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(define_insn "*mov<mode>_aarch64"
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[(set (match_operand:HFBF 0 "nonimmediate_operand" "=w,w , w,?r,w,w ,w ,w,m,r,m ,r")
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(match_operand:HFBF 1 "general_operand" "Y ,?rY,?r, w,w,Ufc,Uvi,m,w,m,rY,r"))]
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[(set (match_operand:HFBF 0 "nonimmediate_operand" "=w,w ,w ,w ,?r,?r,w,w,w ,w ,w,m,r,m ,r")
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(match_operand:HFBF 1 "general_operand" "Y ,?rY,?r,?rY, w, w,w,w,Ufc,Uvi,m,w,m,rY,r"))]
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"TARGET_FLOAT && (register_operand (operands[0], <MODE>mode)
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|| aarch64_reg_or_fp_zero (operands[1], <MODE>mode))"
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"@
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movi\\t%0.4h, #0
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fmov\\t%h0, %w1
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dup\\t%w0.4h, %w1
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fmov\\t%s0, %w1
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umov\\t%w0, %1.h[0]
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fmov\\t%w0, %s1
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mov\\t%0.h[0], %1.h[0]
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fmov\\t%s0, %s1
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fmov\\t%h0, %1
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* return aarch64_output_scalar_simd_mov_immediate (operands[1], HImode);
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ldr\\t%h0, %1
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@ -1469,9 +1473,10 @@
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ldrh\\t%w0, %1
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strh\\t%w1, %0
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mov\\t%w0, %w1"
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[(set_attr "type" "neon_move,f_mcr,neon_move,neon_to_gp, neon_move,fconsts, \
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neon_move,f_loads,f_stores,load_4,store_4,mov_reg")
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(set_attr "arch" "simd,fp16,simd,simd,simd,fp16,simd,*,*,*,*,*")]
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[(set_attr "type" "neon_move,f_mcr,neon_move,f_mcr,neon_to_gp,f_mrc,
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neon_move,fmov,fconsts,neon_move,f_loads,f_stores,
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load_4,store_4,mov_reg")
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(set_attr "arch" "simd,fp16,simd,*,simd,*,simd,*,fp16,simd,*,*,*,*,*")]
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)
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(define_insn "*mov<mode>_aarch64"
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@ -1524,10 +1529,11 @@
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(define_split
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[(set (match_operand:GPF_HF 0 "nonimmediate_operand")
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(match_operand:GPF_HF 1 "general_operand"))]
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(match_operand:GPF_HF 1 "const_double_operand"))]
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"can_create_pseudo_p ()
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&& !aarch64_can_const_movi_rtx_p (operands[1], <MODE>mode)
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&& !aarch64_float_const_representable_p (operands[1])
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&& !aarch64_float_const_zero_rtx_p (operands[1])
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&& aarch64_float_const_rtx_p (operands[1])"
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[(const_int 0)]
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{
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53
gcc/testsuite/gcc.target/aarch64/movdf_1.c
Normal file
53
gcc/testsuite/gcc.target/aarch64/movdf_1.c
Normal file
@ -0,0 +1,53 @@
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/* { dg-do assemble } */
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/* { dg-options "-O --save-temps" } */
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/* { dg-final { check-function-bodies "**" "" "" } } */
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#pragma GCC target "+nothing+nosimd+fp"
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/*
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** fpr_to_fpr:
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** fmov d0, d1
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** ret
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*/
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double
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fpr_to_fpr (double q0, double q1)
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{
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return q1;
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}
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/*
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** gpr_to_fpr:
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** fmov d0, x0
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** ret
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*/
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double
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gpr_to_fpr ()
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{
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register double x0 asm ("x0");
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asm volatile ("" : "=r" (x0));
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return x0;
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}
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/*
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** zero_to_fpr:
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** fmov d0, xzr
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** ret
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*/
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double
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zero_to_fpr ()
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{
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return 0;
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}
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/*
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** fpr_to_gpr:
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** fmov x0, d0
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** ret
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*/
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void
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fpr_to_gpr (double q0)
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{
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register double x0 asm ("x0");
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x0 = q0;
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asm volatile ("" :: "r" (x0));
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}
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61
gcc/testsuite/gcc.target/aarch64/movdi_2.c
Normal file
61
gcc/testsuite/gcc.target/aarch64/movdi_2.c
Normal file
@ -0,0 +1,61 @@
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/* { dg-do assemble } */
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/* { dg-options "-O --save-temps" } */
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/* { dg-final { check-function-bodies "**" "" "" } } */
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#pragma GCC target "+nothing+nosimd+fp"
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#include <stdint.h>
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/*
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** fpr_to_fpr:
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** fmov d0, d1
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** ret
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*/
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void
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fpr_to_fpr (void)
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{
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register uint64_t q0 asm ("q0");
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register uint64_t q1 asm ("q1");
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asm volatile ("" : "=w" (q1));
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q0 = q1;
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asm volatile ("" :: "w" (q0));
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}
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/*
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** gpr_to_fpr:
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** fmov d0, x0
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** ret
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*/
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void
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gpr_to_fpr (uint64_t x0)
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{
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register uint64_t q0 asm ("q0");
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q0 = x0;
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asm volatile ("" :: "w" (q0));
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}
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/*
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** zero_to_fpr:
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** fmov d0, xzr
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** ret
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*/
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void
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zero_to_fpr ()
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{
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register uint64_t q0 asm ("q0");
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q0 = 0;
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asm volatile ("" :: "w" (q0));
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}
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/*
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** fpr_to_gpr:
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** fmov x0, d0
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** ret
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*/
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uint64_t
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fpr_to_gpr ()
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{
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register uint64_t q0 asm ("q0");
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asm volatile ("" : "=w" (q0));
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return q0;
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}
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53
gcc/testsuite/gcc.target/aarch64/movhf_1.c
Normal file
53
gcc/testsuite/gcc.target/aarch64/movhf_1.c
Normal file
@ -0,0 +1,53 @@
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/* { dg-do assemble } */
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/* { dg-options "-O --save-temps" } */
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/* { dg-final { check-function-bodies "**" "" "" } } */
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#pragma GCC target "+nothing+nosimd+fp"
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/*
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** fpr_to_fpr:
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** fmov s0, s1
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** ret
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*/
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_Float16
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fpr_to_fpr (_Float16 q0, _Float16 q1)
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{
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return q1;
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}
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/*
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** gpr_to_fpr:
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** fmov s0, w0
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** ret
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*/
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_Float16
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gpr_to_fpr ()
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{
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register _Float16 w0 asm ("w0");
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asm volatile ("" : "=r" (w0));
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return w0;
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}
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/*
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** zero_to_fpr:
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** fmov s0, wzr
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** ret
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*/
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_Float16
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zero_to_fpr ()
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{
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return 0;
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}
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/*
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** fpr_to_gpr:
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** fmov w0, s0
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** ret
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*/
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void
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fpr_to_gpr (_Float16 q0)
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{
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register _Float16 w0 asm ("w0");
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w0 = q0;
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asm volatile ("" :: "r" (w0));
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}
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61
gcc/testsuite/gcc.target/aarch64/movhi_1.c
Normal file
61
gcc/testsuite/gcc.target/aarch64/movhi_1.c
Normal file
@ -0,0 +1,61 @@
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/* { dg-do assemble } */
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/* { dg-options "-O --save-temps" } */
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/* { dg-final { check-function-bodies "**" "" "" } } */
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#pragma GCC target "+nothing+nosimd+fp"
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#include <stdint.h>
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/*
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** fpr_to_fpr:
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** fmov s0, s1
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** ret
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*/
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void
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fpr_to_fpr (void)
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{
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register uint16_t q0 asm ("q0");
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register uint16_t q1 asm ("q1");
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asm volatile ("" : "=w" (q1));
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q0 = q1;
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asm volatile ("" :: "w" (q0));
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}
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/*
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** gpr_to_fpr:
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** fmov s0, w0
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** ret
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*/
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void
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gpr_to_fpr (uint16_t w0)
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{
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register uint16_t q0 asm ("q0");
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q0 = w0;
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asm volatile ("" :: "w" (q0));
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}
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/*
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** zero_to_fpr:
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** fmov s0, wzr
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** ret
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*/
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void
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zero_to_fpr ()
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{
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register uint16_t q0 asm ("q0");
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q0 = 0;
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asm volatile ("" :: "w" (q0));
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}
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/*
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** fpr_to_gpr:
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** fmov w0, s0
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** ret
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*/
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uint16_t
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fpr_to_gpr ()
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{
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register uint16_t q0 asm ("q0");
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asm volatile ("" : "=w" (q0));
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return q0;
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}
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61
gcc/testsuite/gcc.target/aarch64/movqi_1.c
Normal file
61
gcc/testsuite/gcc.target/aarch64/movqi_1.c
Normal file
@ -0,0 +1,61 @@
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/* { dg-do assemble } */
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/* { dg-options "-O --save-temps" } */
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/* { dg-final { check-function-bodies "**" "" "" } } */
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#pragma GCC target "+nothing+nosimd+fp"
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#include <stdint.h>
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/*
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** fpr_to_fpr:
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** fmov s0, s1
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** ret
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*/
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void
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fpr_to_fpr (void)
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{
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register uint8_t q0 asm ("q0");
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register uint8_t q1 asm ("q1");
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asm volatile ("" : "=w" (q1));
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q0 = q1;
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asm volatile ("" :: "w" (q0));
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}
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/*
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** gpr_to_fpr:
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** fmov s0, w0
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** ret
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*/
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void
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gpr_to_fpr (uint8_t w0)
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{
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register uint8_t q0 asm ("q0");
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q0 = w0;
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asm volatile ("" :: "w" (q0));
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}
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/*
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** zero_to_fpr:
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** fmov s0, wzr
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** ret
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*/
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void
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zero_to_fpr ()
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{
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register uint8_t q0 asm ("q0");
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q0 = 0;
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asm volatile ("" :: "w" (q0));
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}
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/*
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** fpr_to_gpr:
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** fmov w0, s0
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** ret
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*/
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uint8_t
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fpr_to_gpr ()
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{
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register uint8_t q0 asm ("q0");
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asm volatile ("" : "=w" (q0));
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return q0;
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}
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53
gcc/testsuite/gcc.target/aarch64/movsf_1.c
Normal file
53
gcc/testsuite/gcc.target/aarch64/movsf_1.c
Normal file
@ -0,0 +1,53 @@
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-options "-O --save-temps" } */
|
||||
/* { dg-final { check-function-bodies "**" "" "" } } */
|
||||
|
||||
#pragma GCC target "+nothing+nosimd+fp"
|
||||
|
||||
/*
|
||||
** fpr_to_fpr:
|
||||
** fmov s0, s1
|
||||
** ret
|
||||
*/
|
||||
float
|
||||
fpr_to_fpr (float q0, float q1)
|
||||
{
|
||||
return q1;
|
||||
}
|
||||
|
||||
/*
|
||||
** gpr_to_fpr:
|
||||
** fmov s0, w0
|
||||
** ret
|
||||
*/
|
||||
float
|
||||
gpr_to_fpr ()
|
||||
{
|
||||
register float w0 asm ("w0");
|
||||
asm volatile ("" : "=r" (w0));
|
||||
return w0;
|
||||
}
|
||||
|
||||
/*
|
||||
** zero_to_fpr:
|
||||
** fmov s0, wzr
|
||||
** ret
|
||||
*/
|
||||
float
|
||||
zero_to_fpr ()
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
** fpr_to_gpr:
|
||||
** fmov w0, s0
|
||||
** ret
|
||||
*/
|
||||
void
|
||||
fpr_to_gpr (float q0)
|
||||
{
|
||||
register float w0 asm ("w0");
|
||||
w0 = q0;
|
||||
asm volatile ("" :: "r" (w0));
|
||||
}
|
||||
61
gcc/testsuite/gcc.target/aarch64/movsi_1.c
Normal file
61
gcc/testsuite/gcc.target/aarch64/movsi_1.c
Normal file
@ -0,0 +1,61 @@
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-options "-O --save-temps" } */
|
||||
/* { dg-final { check-function-bodies "**" "" "" } } */
|
||||
|
||||
#pragma GCC target "+nothing+nosimd+fp"
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
** fpr_to_fpr:
|
||||
** fmov s0, s1
|
||||
** ret
|
||||
*/
|
||||
void
|
||||
fpr_to_fpr (void)
|
||||
{
|
||||
register uint32_t q0 asm ("q0");
|
||||
register uint32_t q1 asm ("q1");
|
||||
asm volatile ("" : "=w" (q1));
|
||||
q0 = q1;
|
||||
asm volatile ("" :: "w" (q0));
|
||||
}
|
||||
|
||||
/*
|
||||
** gpr_to_fpr:
|
||||
** fmov s0, w0
|
||||
** ret
|
||||
*/
|
||||
void
|
||||
gpr_to_fpr (uint32_t w0)
|
||||
{
|
||||
register uint32_t q0 asm ("q0");
|
||||
q0 = w0;
|
||||
asm volatile ("" :: "w" (q0));
|
||||
}
|
||||
|
||||
/*
|
||||
** zero_to_fpr:
|
||||
** fmov s0, wzr
|
||||
** ret
|
||||
*/
|
||||
void
|
||||
zero_to_fpr ()
|
||||
{
|
||||
register uint32_t q0 asm ("q0");
|
||||
q0 = 0;
|
||||
asm volatile ("" :: "w" (q0));
|
||||
}
|
||||
|
||||
/*
|
||||
** fpr_to_gpr:
|
||||
** fmov w0, s0
|
||||
** ret
|
||||
*/
|
||||
uint32_t
|
||||
fpr_to_gpr ()
|
||||
{
|
||||
register uint32_t q0 asm ("q0");
|
||||
asm volatile ("" : "=w" (q0));
|
||||
return q0;
|
||||
}
|
||||
81
gcc/testsuite/gcc.target/aarch64/movtf_2.c
Normal file
81
gcc/testsuite/gcc.target/aarch64/movtf_2.c
Normal file
@ -0,0 +1,81 @@
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-require-effective-target large_long_double } */
|
||||
/* { dg-options "-O -mtune=neoverse-v1 --save-temps" } */
|
||||
/* { dg-final { check-function-bodies "**" "" "" } } */
|
||||
|
||||
#pragma GCC target "+nothing+nosimd+fp"
|
||||
|
||||
/*
|
||||
** fpr_to_fpr:
|
||||
** sub sp, sp, #16
|
||||
** str q1, \[sp\]
|
||||
** ldr q0, \[sp\]
|
||||
** add sp, sp, #?16
|
||||
** ret
|
||||
*/
|
||||
long double
|
||||
fpr_to_fpr (long double q0, long double q1)
|
||||
{
|
||||
return q1;
|
||||
}
|
||||
|
||||
/*
|
||||
** gpr_to_fpr: { target aarch64_little_endian }
|
||||
** fmov d0, x0
|
||||
** fmov v0.d\[1\], x1
|
||||
** ret
|
||||
*/
|
||||
/*
|
||||
** gpr_to_fpr: { target aarch64_big_endian }
|
||||
** fmov d0, x1
|
||||
** fmov v0.d\[1\], x0
|
||||
** ret
|
||||
*/
|
||||
long double
|
||||
gpr_to_fpr ()
|
||||
{
|
||||
register long double x0 asm ("x0");
|
||||
asm volatile ("" : "=r" (x0));
|
||||
return x0;
|
||||
}
|
||||
|
||||
/*
|
||||
** zero_to_fpr:
|
||||
** fmov s0, wzr
|
||||
** ret
|
||||
*/
|
||||
long double
|
||||
zero_to_fpr ()
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
** fpr_to_gpr: { target aarch64_little_endian }
|
||||
** (
|
||||
** fmov x0, d0
|
||||
** fmov x1, v0.d\[1\]
|
||||
** |
|
||||
** fmov x1, v0.d\[1\]
|
||||
** fmov x0, d0
|
||||
** )
|
||||
** ret
|
||||
*/
|
||||
/*
|
||||
** fpr_to_gpr: { target aarch64_big_endian }
|
||||
** (
|
||||
** fmov x1, d0
|
||||
** fmov x0, v0.d\[1\]
|
||||
** |
|
||||
** fmov x0, v0.d\[1\]
|
||||
** fmov x1, d0
|
||||
** )
|
||||
** ret
|
||||
*/
|
||||
void
|
||||
fpr_to_gpr (long double q0)
|
||||
{
|
||||
register long double x0 asm ("x0");
|
||||
x0 = q0;
|
||||
asm volatile ("" :: "r" (x0));
|
||||
}
|
||||
86
gcc/testsuite/gcc.target/aarch64/movti_2.c
Normal file
86
gcc/testsuite/gcc.target/aarch64/movti_2.c
Normal file
@ -0,0 +1,86 @@
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-options "-O -mtune=neoverse-v1 --save-temps" } */
|
||||
/* { dg-final { check-function-bodies "**" "" "" } } */
|
||||
|
||||
#pragma GCC target "+nothing+nosimd+fp"
|
||||
|
||||
/*
|
||||
** fpr_to_fpr:
|
||||
** sub sp, sp, #16
|
||||
** str q1, \[sp\]
|
||||
** ldr q0, \[sp\]
|
||||
** add sp, sp, #?16
|
||||
** ret
|
||||
*/
|
||||
void
|
||||
fpr_to_fpr (void)
|
||||
{
|
||||
register __int128_t q0 asm ("q0");
|
||||
register __int128_t q1 asm ("q1");
|
||||
asm volatile ("" : "=w" (q1));
|
||||
q0 = q1;
|
||||
asm volatile ("" :: "w" (q0));
|
||||
}
|
||||
|
||||
/*
|
||||
** gpr_to_fpr: { target aarch64_little_endian }
|
||||
** fmov d0, x0
|
||||
** fmov v0.d\[1\], x1
|
||||
** ret
|
||||
*/
|
||||
/*
|
||||
** gpr_to_fpr: { target aarch64_big_endian }
|
||||
** fmov d0, x1
|
||||
** fmov v0.d\[1\], x0
|
||||
** ret
|
||||
*/
|
||||
void
|
||||
gpr_to_fpr (__int128_t x0)
|
||||
{
|
||||
register __int128_t q0 asm ("q0");
|
||||
q0 = x0;
|
||||
asm volatile ("" :: "w" (q0));
|
||||
}
|
||||
|
||||
/*
|
||||
** zero_to_fpr:
|
||||
** fmov d0, xzr
|
||||
** ret
|
||||
*/
|
||||
void
|
||||
zero_to_fpr ()
|
||||
{
|
||||
register __int128_t q0 asm ("q0");
|
||||
q0 = 0;
|
||||
asm volatile ("" :: "w" (q0));
|
||||
}
|
||||
|
||||
/*
|
||||
** fpr_to_gpr: { target aarch64_little_endian }
|
||||
** (
|
||||
** fmov x0, d0
|
||||
** fmov x1, v0.d\[1\]
|
||||
** |
|
||||
** fmov x1, v0.d\[1\]
|
||||
** fmov x0, d0
|
||||
** )
|
||||
** ret
|
||||
*/
|
||||
/*
|
||||
** fpr_to_gpr: { target aarch64_big_endian }
|
||||
** (
|
||||
** fmov x1, d0
|
||||
** fmov x0, v0.d\[1\]
|
||||
** |
|
||||
** fmov x0, v0.d\[1\]
|
||||
** fmov x1, d0
|
||||
** )
|
||||
** ret
|
||||
*/
|
||||
__int128_t
|
||||
fpr_to_gpr ()
|
||||
{
|
||||
register __int128_t q0 asm ("q0");
|
||||
asm volatile ("" : "=w" (q0));
|
||||
return q0;
|
||||
}
|
||||
82
gcc/testsuite/gcc.target/aarch64/movv16qi_1.c
Normal file
82
gcc/testsuite/gcc.target/aarch64/movv16qi_1.c
Normal file
@ -0,0 +1,82 @@
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-options "-O -mtune=neoverse-v1 --save-temps" } */
|
||||
/* { dg-final { check-function-bodies "**" "" "" } } */
|
||||
|
||||
#pragma GCC target "+nothing+nosimd+fp"
|
||||
|
||||
typedef unsigned char v16qi __attribute__((vector_size(16)));
|
||||
|
||||
/*
|
||||
** fpr_to_fpr:
|
||||
** sub sp, sp, #16
|
||||
** str q1, \[sp\]
|
||||
** ldr q0, \[sp\]
|
||||
** add sp, sp, #?16
|
||||
** ret
|
||||
*/
|
||||
v16qi
|
||||
fpr_to_fpr (v16qi q0, v16qi q1)
|
||||
{
|
||||
return q1;
|
||||
}
|
||||
|
||||
/*
|
||||
** gpr_to_fpr: { target aarch64_little_endian }
|
||||
** fmov d0, x0
|
||||
** fmov v0.d\[1\], x1
|
||||
** ret
|
||||
*/
|
||||
/*
|
||||
** gpr_to_fpr: { target aarch64_big_endian }
|
||||
** fmov d0, x1
|
||||
** fmov v0.d\[1\], x0
|
||||
** ret
|
||||
*/
|
||||
v16qi
|
||||
gpr_to_fpr ()
|
||||
{
|
||||
register v16qi x0 asm ("x0");
|
||||
asm volatile ("" : "=r" (x0));
|
||||
return x0;
|
||||
}
|
||||
|
||||
/*
|
||||
** zero_to_fpr:
|
||||
** fmov d0, xzr
|
||||
** ret
|
||||
*/
|
||||
v16qi
|
||||
zero_to_fpr ()
|
||||
{
|
||||
return (v16qi) {};
|
||||
}
|
||||
|
||||
/*
|
||||
** fpr_to_gpr: { target aarch64_little_endian }
|
||||
** (
|
||||
** fmov x0, d0
|
||||
** fmov x1, v0.d\[1\]
|
||||
** |
|
||||
** fmov x1, v0.d\[1\]
|
||||
** fmov x0, d0
|
||||
** )
|
||||
** ret
|
||||
*/
|
||||
/*
|
||||
** fpr_to_gpr: { target aarch64_big_endian }
|
||||
** (
|
||||
** fmov x1, d0
|
||||
** fmov x0, v0.d\[1\]
|
||||
** |
|
||||
** fmov x0, v0.d\[1\]
|
||||
** fmov x1, d0
|
||||
** )
|
||||
** ret
|
||||
*/
|
||||
void
|
||||
fpr_to_gpr (v16qi q0)
|
||||
{
|
||||
register v16qi x0 asm ("x0");
|
||||
x0 = q0;
|
||||
asm volatile ("" :: "r" (x0));
|
||||
}
|
||||
55
gcc/testsuite/gcc.target/aarch64/movv8qi_1.c
Normal file
55
gcc/testsuite/gcc.target/aarch64/movv8qi_1.c
Normal file
@ -0,0 +1,55 @@
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-options "-O -mtune=neoverse-v1 --save-temps" } */
|
||||
/* { dg-final { check-function-bodies "**" "" "" } } */
|
||||
|
||||
#pragma GCC target "+nothing+nosimd+fp"
|
||||
|
||||
typedef unsigned char v8qi __attribute__((vector_size(8)));
|
||||
|
||||
/*
|
||||
** fpr_to_fpr:
|
||||
** fmov d0, d1
|
||||
** ret
|
||||
*/
|
||||
v8qi
|
||||
fpr_to_fpr (v8qi q0, v8qi q1)
|
||||
{
|
||||
return q1;
|
||||
}
|
||||
|
||||
/*
|
||||
** gpr_to_fpr:
|
||||
** fmov d0, x0
|
||||
** ret
|
||||
*/
|
||||
v8qi
|
||||
gpr_to_fpr ()
|
||||
{
|
||||
register v8qi x0 asm ("x0");
|
||||
asm volatile ("" : "=r" (x0));
|
||||
return x0;
|
||||
}
|
||||
|
||||
/*
|
||||
** zero_to_fpr:
|
||||
** fmov d0, xzr
|
||||
** ret
|
||||
*/
|
||||
v8qi
|
||||
zero_to_fpr ()
|
||||
{
|
||||
return (v8qi) {};
|
||||
}
|
||||
|
||||
/*
|
||||
** fpr_to_gpr:
|
||||
** fmov x0, d0
|
||||
** ret
|
||||
*/
|
||||
void
|
||||
fpr_to_gpr (v8qi q0)
|
||||
{
|
||||
register v8qi x0 asm ("x0");
|
||||
x0 = q0;
|
||||
asm volatile ("" :: "r" (x0));
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user