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Remove -mfloat32, -mfloat64 switches from pdp11 target.

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* config/pdp11/pdp11.h (FLOAT_TYPE_SIZE): Always 32.
    * config/pdp11/pdp11.opt (mfloat32): Remove.
    (mfloat64): Remove.
    * doc/invoke.texi (pdp11 -mfloat32): Remove:
    (pdp11 -mfloat64): Remove.

From-SVN: r264881
This commit is contained in:
Paul Koning 2018-10-05 13:37:56 -04:00 committed by Paul Koning
parent 9a85d982cc
commit d5a9895595
4 changed files with 17 additions and 29 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2018-10-05 Paul Koning <ni1d@arrl.net>
* config/pdp11/pdp11.h (FLOAT_TYPE_SIZE): Always 32.
* config/pdp11/pdp11.opt (mfloat32): Remove.
(mfloat64): Remove.
* doc/invoke.texi (pdp11 -mfloat32): Remove:
(pdp11 -mfloat64): Remove.
2018-10-05 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*cmpxf_i387): Change operand 2 predicate

17
gcc/config/pdp11/pdp11.h
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@ -59,12 +59,14 @@ along with GCC; see the file COPYING3. If not see
#define LONG_TYPE_SIZE 32
#define LONG_LONG_TYPE_SIZE 64
/* if we set FLOAT_TYPE_SIZE to 32, we could have the benefit
of saving core for huge arrays - the definitions are
already in md - but floats can never reside in
an FPU register - we keep the FPU in double float mode
all the time !! */
#define FLOAT_TYPE_SIZE (TARGET_FLOAT32 ? 32 : 64)
/* In earlier versions, FLOAT_TYPE_SIZE was selectable as 32 or 64,
but that conflicts with Fortran language rules. Since there is no
obvious reason why we should have that feature -- other targets
generally don't have float and double the same size -- I've removed
it. Note that it continues to be true (for now) that arithmetic is
always done with 64-bit values, i.e., the FPU is always in "double"
mode. */
#define FLOAT_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
#define LONG_DOUBLE_TYPE_SIZE 64
@ -200,12 +202,11 @@ extern const struct real_format pdp11_d_format;
MUL_REGS are used for odd numbered regs, to use in 16-bit multiplication
(even numbered do 32-bit multiply)
LMUL_REGS long multiply registers (even numbered regs )
(don't need them, all 32-bit regs are even numbered!)
GENERAL_REGS is all cpu
LOAD_FPU_REGS is the first four cpu regs, they are easier to load
NO_LOAD_FPU_REGS is ac4 and ac5, currently - difficult to load them
FPU_REGS is all fpu regs
CC_REGS is the condition codes (CPU and FPU)
*/
enum reg_class

8
gcc/config/pdp11/pdp11.opt
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@ -42,14 +42,6 @@ mgnu-asm
Target RejectNegative Report Mask(GNU_ASM) Negative(munix-asm)
Use the GNU assembler syntax.
mfloat32
Target Report Mask(FLOAT32)
Use 32 bit float.
mfloat64
Target Report InverseMask(FLOAT32, FLOAT64)
Use 64 bit float.
mfpu
Target RejectNegative Report Mask(FPU)
Use hardware floating point.

13
gcc/doc/invoke.texi
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@ -1007,7 +1007,6 @@ Objective-C and Objective-C++ Dialects}.
@emph{PDP-11 Options}
@gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol
-mint32 -mno-int16 -mint16 -mno-int32 @gol
-mfloat32 -mno-float64 -mfloat64 -mno-float32 @gol
-msplit -munix-asm -mdec-asm -mgnu-asm -mlra}
@emph{picoChip Options}
@ -22722,18 +22721,6 @@ Use 16-bit @code{int}. This is the default.
@opindex mno-int16
Use 32-bit @code{int}.
@item -mfloat64
@itemx -mno-float32
@opindex mfloat64
@opindex mno-float32
Use 64-bit @code{float}. This is the default.
@item -mfloat32
@itemx -mno-float64
@opindex mfloat32
@opindex mno-float64
Use 32-bit @code{float}.
@item -msplit
@opindex msplit
Target has split instruction and data space. Implies -m45.