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Fix misscheduling of epilogue predicate register restore.
* config/ia64/ia64.c (rtx_needs_barrier, case UNSPEC): Move case 6... (rtx_needs_barrier, case UNSPEC_VOLATILE): to here. * config/ia64/ia64.md (pr_restore): Change UNSPEC to UNSPEC_VOLATILE. From-SVN: r32714
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@ -1,3 +1,9 @@
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Thu Mar 23 11:34:39 2000 Jim Wilson <wilson@cygnus.com>
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* config/ia64/ia64.c (rtx_needs_barrier, case UNSPEC): Move case 6...
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(rtx_needs_barrier, case UNSPEC_VOLATILE): to here.
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* config/ia64/ia64.md (pr_restore): Change UNSPEC to UNSPEC_VOLATILE.
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Thu Mar 23 16:04:40 2000 Andrew Haley <aph@cygnus.com>
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* config/mips/mips.md (movdf_internal1a): Delete (set 'f', 'F')
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@ -2421,16 +2421,7 @@ rtx_needs_barrier (x, flags, pred)
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need_barrier |= rws_access_reg (i, flags, pred);
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break;
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case 6: /* mov pr= */
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/* This writes all predicate registers. */
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new_flags.is_write = 1;
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/* We need to skip by two, because rws_access_reg always writes
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to two predicate registers at a time. */
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/* ??? Strictly speaking, we shouldn't be counting writes to pr0. */
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for (i = PR_REG (0); i < PR_REG (64); i += 2)
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need_barrier |= rws_access_reg (i, new_flags, pred);
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break;
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case 6:
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case 7:
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abort ();
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@ -2486,6 +2477,16 @@ rtx_needs_barrier (x, flags, pred)
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need_barrier = rws_access_reg (REG_AR_PFS, new_flags, pred);
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break;
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case 6: /* mov pr= */
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/* This writes all predicate registers. */
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new_flags.is_write = 1;
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/* We need to skip by two, because rws_access_reg always writes
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to two predicate registers at a time. */
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/* ??? Strictly speaking, we shouldn't be counting writes to pr0. */
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for (i = PR_REG (0); i < PR_REG (64); i += 2)
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need_barrier |= rws_access_reg (i, new_flags, pred);
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break;
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default:
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abort ();
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}
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@ -3049,8 +3049,11 @@
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"mov %0 = pr"
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[(set_attr "type" "I")])
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;; ??? This is volatile to prevent it from being moved before a conditional
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;; expression that calculates the return value.
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(define_insn "pr_restore"
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[(unspec [(const_int 0)] 6)
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[(unspec_volatile [(const_int 0)] 6)
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(use (match_operand:DI 0 "register_operand" "r"))]
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""
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"mov pr = %0, -1"
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