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i386: Optimize {,v}{,p}movmsk{b,ps,pd} followed by sign extension [PR91824]
Some time ago, patterns were added to optimize move mask followed by zero extension from 32 bits to 64 bit. As the testcase shows, the intrinsics actually return int, not unsigned int, so it will happen quite often that one actually needs sign extension instead of zero extension. Except for vpmovmskb with 256-bit operand, sign vs. zero extension doesn't make a difference, as we know the bit 31 will not be set (the source will have 2 or 4 doubles, 4 or 8 floats or 16 or 32 chars). So, for the floating point patterns, this patch just uses a code iterator so that we handle both zero extend and sign extend, and for the byte one adds a separate pattern for the 128-bit operand. 2020-01-30 Jakub Jelinek <jakub@redhat.com> PR target/91824 * config/i386/sse.md (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): Renamed to ... (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): ... this. Use any_extend code iterator instead of always zero_extend. (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_lt): Renamed to ... (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): ... this. Use any_extend code iterator instead of always zero_extend. (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_shift): Renamed to ... (*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): ... this. Use any_extend code iterator instead of always zero_extend. (*sse2_pmovmskb_ext): New define_insn. (*sse2_pmovmskb_ext_lt): New define_insn_and_split. * gcc.target/i386/pr91824-2.c: New test.
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Jakub Jelinek
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@ -1,5 +1,19 @@
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2020-01-30 Jakub Jelinek <jakub@redhat.com>
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PR target/91824
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* config/i386/sse.md
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(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext): Renamed to ...
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(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): ... this. Use
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any_extend code iterator instead of always zero_extend.
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(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_lt): Renamed to ...
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(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt): ... this.
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Use any_extend code iterator instead of always zero_extend.
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(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_shift): Renamed to ...
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(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift): ... this.
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Use any_extend code iterator instead of always zero_extend.
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(*sse2_pmovmskb_ext): New define_insn.
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(*sse2_pmovmskb_ext_lt): New define_insn_and_split.
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PR target/91824
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* config/i386/i386.md (*popcountsi2_zext): New define_insn_and_split.
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(*popcountsi2_zext_falsedep): New define_insn.
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@ -15815,9 +15815,9 @@
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "<MODE>")])
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(define_insn "*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext"
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(define_insn "*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI
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(any_extend:DI
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(unspec:SI
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[(match_operand:VF_128_256 1 "register_operand" "x")]
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UNSPEC_MOVMSK)))]
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@ -15844,9 +15844,9 @@
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "<MODE>")])
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(define_insn_and_split "*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_lt"
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(define_insn_and_split "*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_lt"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI
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(any_extend:DI
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(unspec:SI
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[(lt:VF_128_256
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(match_operand:<sseintvecmode> 1 "register_operand" "x")
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@ -15856,7 +15856,7 @@
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"#"
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"&& reload_completed"
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[(set (match_dup 0)
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(zero_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK)))]
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(any_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK)))]
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"operands[1] = gen_lowpart (<MODE>mode, operands[1]);"
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[(set_attr "type" "ssemov")
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(set_attr "prefix" "maybe_vex")
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@ -15880,9 +15880,9 @@
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "<MODE>")])
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(define_insn_and_split "*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_zext_shift"
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(define_insn_and_split "*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext_shift"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI
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(any_extend:DI
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(unspec:SI
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[(subreg:VF_128_256
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(ashiftrt:<sseintvecmode>
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@ -15893,7 +15893,7 @@
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"#"
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"&& reload_completed"
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[(set (match_dup 0)
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(zero_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK)))]
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(any_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK)))]
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"operands[1] = gen_lowpart (<MODE>mode, operands[1]);"
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[(set_attr "type" "ssemov")
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(set_attr "prefix" "maybe_vex")
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@ -15932,6 +15932,23 @@
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "SI")])
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(define_insn "*sse2_pmovmskb_ext"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI
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(unspec:SI
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[(match_operand:V16QI 1 "register_operand" "x")]
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UNSPEC_MOVMSK)))]
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"TARGET_64BIT && TARGET_SSE2"
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"%vpmovmskb\t{%1, %k0|%k0, %1}"
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[(set_attr "type" "ssemov")
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(set (attr "prefix_data16")
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(if_then_else
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(match_test "TARGET_AVX")
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(const_string "*")
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(const_string "1")))
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "SI")])
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(define_insn_and_split "*<sse2_avx2>_pmovmskb_lt"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI
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@ -15975,6 +15992,28 @@
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "SI")])
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(define_insn_and_split "*sse2_pmovmskb_ext_lt"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI
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(unspec:SI
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[(lt:V16QI (match_operand:V16QI 1 "register_operand" "x")
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(match_operand:V16QI 2 "const0_operand" "C"))]
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UNSPEC_MOVMSK)))]
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"TARGET_64BIT && TARGET_SSE2"
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"#"
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""
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[(set (match_dup 0)
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(sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_MOVMSK)))]
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""
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[(set_attr "type" "ssemov")
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(set (attr "prefix_data16")
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(if_then_else
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(match_test "TARGET_AVX")
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(const_string "*")
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(const_string "1")))
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "SI")])
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(define_expand "sse2_maskmovdqu"
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[(set (match_operand:V16QI 0 "memory_operand")
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(unspec:V16QI [(match_operand:V16QI 1 "register_operand")
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@ -1,5 +1,8 @@
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2020-01-30 Jakub Jelinek <jakub@redhat.com>
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PR target/91824
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* gcc.target/i386/pr91824-2.c: New test.
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PR target/91824
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* gcc.target/i386/pr91824-1.c: New test.
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73
gcc/testsuite/gcc.target/i386/pr91824-2.c
Normal file
73
gcc/testsuite/gcc.target/i386/pr91824-2.c
Normal file
@ -0,0 +1,73 @@
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/* PR target/91824 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -mavx2" } */
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/* { dg-final { scan-assembler-not "cltq" } } */
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/* { dg-final { scan-assembler-not "movl\t%eax, %eax" } } */
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#include <x86intrin.h>
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unsigned long long
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f1 (__m128i x)
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{
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return _mm_movemask_epi8 (x);
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}
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unsigned long long
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f2 (__m128i x)
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{
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return (unsigned) _mm_movemask_epi8 (x);
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}
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unsigned long long
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f3 (__m128 x)
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{
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return _mm_movemask_ps (x);
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}
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unsigned long long
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f4 (__m128 x)
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{
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return (unsigned) _mm_movemask_ps (x);
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}
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unsigned long long
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f5 (__m128d x)
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{
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return _mm_movemask_pd (x);
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}
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unsigned long long
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f6 (__m128d x)
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{
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return (unsigned) _mm_movemask_pd (x);
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}
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unsigned long long
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f7 (__m256 x)
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{
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return _mm256_movemask_ps (x);
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}
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unsigned long long
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f8 (__m256 x)
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{
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return (unsigned) _mm256_movemask_ps (x);
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}
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unsigned long long
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f9 (__m256d x)
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{
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return _mm256_movemask_pd (x);
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}
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unsigned long long
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f10 (__m256d x)
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{
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return (unsigned) _mm256_movemask_pd (x);
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}
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unsigned long long
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f11 (__m256i x)
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{
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return (unsigned) _mm256_movemask_epi8 (x);
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}
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