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driver-i386.c (host_detect_local_cpu): Set PROCESSOR_K8 for signature_CENTAUR_ebx with has_longmode.
* config/i386/driver-i386.c (host_detect_local_cpu): Set PROCESSOR_K8 for signature_CENTAUR_ebx with has_longmode. <case PROCESSOR_K8>: Pass nano-3000, nano, eden-x2 or k8 for signature_CENTAUR_ebx. * config/i386/i386.c (ix86_option_override_internal): Add definitions for VIA c7, samuel-2, nehemiah, esther, eden-x2, eden-x4, nano, nano-1000, nano-2000, nano-3000, nano-x2 and nano-x4. * doc/invoke.texi: Document new VIA -march entries. From-SVN: r237534
This commit is contained in:
Jocelyn Mayer
Uros Bizjak
parent
68fa96d625
commit
d3606ee3ea
@ -1,3 +1,14 @@
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2016-06-16 Jocelyn Mayer <l_indien@magic.fr>
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* config/i386/driver-i386.c (host_detect_local_cpu): Set
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PROCESSOR_K8 for signature_CENTAUR_ebx with has_longmode.
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<case PROCESSOR_K8>: Pass nano-3000, nano, eden-x2 or k8 for
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signature_CENTAUR_ebx.
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* config/i386/i386.c (ix86_option_override_internal): Add
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definitions for VIA c7, samuel-2, nehemiah, esther, eden-x2, eden-x4,
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nano, nano-1000, nano-2000, nano-3000, nano-x2 and nano-x4.
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* doc/invoke.texi: Document new VIA -march entries.
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2016-06-16 Martin Liska <mliska@suse.cz>
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* predict.def: Add fortran loop preheader predictor.
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@ -651,7 +651,9 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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break;
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case 6:
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if (model > 9 || has_longmode)
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if (has_longmode)
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processor = PROCESSOR_K8;
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else if (model > 9)
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/* Use the default detection procedure. */
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;
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else if (model == 9)
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@ -869,9 +871,30 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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cpu = "athlon";
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break;
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case PROCESSOR_K8:
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if (arch && has_sse3)
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cpu = "k8-sse3";
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if (arch)
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{
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if (vendor == signature_CENTAUR_ebx)
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{
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if (has_sse4_1)
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/* Nano 3000 | Nano dual / quad core | Eden X4 */
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cpu = "nano-3000";
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else if (has_ssse3)
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/* Nano 1000 | Nano 2000 */
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cpu = "nano";
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else if (has_sse3)
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/* Eden X2 */
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cpu = "eden-x2";
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else
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/* Default to k8 */
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cpu = "k8";
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}
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else if (has_sse3)
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cpu = "k8-sse3";
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else
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cpu = "k8";
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}
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else
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/* For -mtune, we default to -mtune=k8 */
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cpu = "k8";
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break;
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case PROCESSOR_AMDFAM10:
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@ -4783,8 +4783,15 @@ ix86_option_override_internal (bool main_args_p,
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{"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
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{"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
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{"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
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{"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
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{"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
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PTA_MMX | PTA_SSE | PTA_FXSR},
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{"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
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PTA_MMX | PTA_SSE | PTA_FXSR},
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{"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
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PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
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{"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
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PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
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{"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
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{"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
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{"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
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@ -4843,6 +4850,29 @@ ix86_option_override_internal (bool main_args_p,
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PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_PRFCHW | PTA_FXSR},
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{"x86-64", PROCESSOR_K8, CPU_K8,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
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{"eden-x2", PROCESSOR_K8, CPU_K8,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
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{"nano", PROCESSOR_K8, CPU_K8,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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| PTA_SSSE3 | PTA_FXSR},
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{"nano-1000", PROCESSOR_K8, CPU_K8,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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| PTA_SSSE3 | PTA_FXSR},
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{"nano-2000", PROCESSOR_K8, CPU_K8,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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| PTA_SSSE3 | PTA_FXSR},
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{"nano-3000", PROCESSOR_K8, CPU_K8,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
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{"nano-x2", PROCESSOR_K8, CPU_K8,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
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{"eden-x4", PROCESSOR_K8, CPU_K8,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
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{"nano-x4", PROCESSOR_K8, CPU_K8,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
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{"k8", PROCESSOR_K8, CPU_K8,
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PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
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| PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
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@ -4888,7 +4918,7 @@ ix86_option_override_internal (bool main_args_p,
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| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
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| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
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| PTA_XSAVEOPT | PTA_FSGSBASE},
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{"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
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{"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
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| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
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@ -4905,7 +4935,7 @@ ix86_option_override_internal (bool main_args_p,
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| PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
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| PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
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| PTA_SHA | PTA_LZCNT | PTA_POPCNT},
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{"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
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{"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
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PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
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| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
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| PTA_FXSR | PTA_XSAVE},
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@ -23357,13 +23357,67 @@ IDT WinChip 2 CPU, dealt in same way as i486 with additional MMX and 3DNow!@:
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instruction set support.
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@item c3
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VIA C3 CPU with MMX and 3DNow!@: instruction set support. (No scheduling is
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implemented for this chip.)
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VIA C3 CPU with MMX and 3DNow!@: instruction set support.
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(No scheduling is implemented for this chip.)
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@item c3-2
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VIA C3-2 (Nehemiah/C5XL) CPU with MMX and SSE instruction set support.
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(No scheduling is
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implemented for this chip.)
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(No scheduling is implemented for this chip.)
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@item c7
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VIA C7 (Esther) CPU with MMX, SSE, SSE2 and SSE3 instruction set support.
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(No scheduling is implemented for this chip.)
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@item samuel-2
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VIA Eden Samuel 2 CPU with MMX and 3DNow!@: instruction set support.
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(No scheduling is implemented for this chip.)
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@item nehemiah
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VIA Eden Nehemiah CPU with MMX and SSE instruction set support.
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(No scheduling is implemented for this chip.)
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@item esther
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VIA Eden Esther CPU with MMX, SSE, SSE2 and SSE3 instruction set support.
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(No scheduling is implemented for this chip.)
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@item eden-x2
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VIA Eden X2 CPU with x86-64, MMX, SSE, SSE2 and SSE3 instruction set support.
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(No scheduling is implemented for this chip.)
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@item eden-x4
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VIA Eden X4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2,
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AVX and AVX2 instruction set support.
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(No scheduling is implemented for this chip.)
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@item nano
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Generic VIA Nano CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3
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instruction set support.
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(No scheduling is implemented for this chip.)
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@item nano-1000
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VIA Nano 1xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3
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instruction set support.
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(No scheduling is implemented for this chip.)
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@item nano-2000
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VIA Nano 2xxx CPU with x86-64, MMX, SSE, SSE2, SSE3 and SSSE3
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instruction set support.
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(No scheduling is implemented for this chip.)
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@item nano-3000
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VIA Nano 3xxx CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1
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instruction set support.
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(No scheduling is implemented for this chip.)
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@item nano-x2
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VIA Nano Dual Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1
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instruction set support.
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(No scheduling is implemented for this chip.)
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@item nano-x4
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VIA Nano Quad Core CPU with x86-64, MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1
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instruction set support.
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(No scheduling is implemented for this chip.)
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@item geode
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AMD Geode embedded processor with MMX and 3DNow!@: instruction set support.
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