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Add performance related explanatory comment.

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* config/ia64/ia64.md (insv): Add comment.

From-SVN: r33836
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Jim Wilson 2000-05-11 04:38:29 +00:00 committed by Jim Wilson
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commit d2ba6dcff5
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gcc/ChangeLog
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@ -1,3 +1,7 @@
Wed May 10 21:31:44 2000 Jim Wilson <wilson@cygnus.com>
* config/ia64/ia64.md (insv): Add comment.
2000-05-10 Richard Henderson <rth@cygnus.com>
* Makefile.in (libgcc.a, stmp-multilib): Depend on FPBIT and DPBIT.

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gcc/config/ia64/ia64.md
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@ -684,6 +684,21 @@
DONE;
}
/* We could handle remaining cases by emitting multiple dep
instructions.
If we need more than two dep instructions then we lose. A 6
insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than
mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles,
the latter is 6 cycles on an Itanium (TM) processor, because there is
only one function unit that can execute dep and shr immed.
If we only need two dep instruction, then we still lose.
mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away
the unnecessary mov, this is still undesirable because it will be
hard to optimize, and it creates unnecessary pressure on the I0
function unit. */
FAIL;
#if 0