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re PR target/52908 (xop-mul-1:f9 miscompiled on bulldozer (-mxop))
PR target/52908 * config/i386/sse.md (vec_widen_smult_hi_v4si): Expand using xop_pmacsdqh insn pattern instead of xop_mulv2div2di3_high. (vec_widen_smult_lo_v4si): Expand using xop_pmacsdql insn pattern instead of xop_mulv2div2di3_low. (xop_p<macs>dql): Fix vec_select selector. (xop_p<macs>dqh): Ditto. (xop_mulv2div2di3_low): Remove insn_and_split pattern. (xop_mulv2div2di3_high): Ditto. testsuite/ChangeLog: PR target/52908 * gcc.target/i386/xop-imul32widen-vector.c: Update scan-assembler directive to Scan for vpmuldq, not vpmacsdql. From-SVN: r187354
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Uros Bizjak
Uros Bizjak
parent
c54e713661
commit
d21a7b447a
@ -1,3 +1,15 @@
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2012-05-09 Uros Bizjak <ubizjak@gmail.com>
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PR target/52908
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* config/i386/sse.md (vec_widen_smult_hi_v4si): Expand using
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xop_pmacsdqh insn pattern instead of xop_mulv2div2di3_high.
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(vec_widen_smult_lo_v4si): Expand using xop_pmacsdql insn pattern
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instead of xop_mulv2div2di3_low.
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(xop_p<macs>dql): Fix vec_select selector.
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(xop_p<macs>dqh): Ditto.
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(xop_mulv2div2di3_low): Remove insn_and_split pattern.
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(xop_mulv2div2di3_high): Ditto.
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2012-05-09 Manuel López-Ibáñez <manu@gcc.gnu.org>
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* doc/extend.texi (Function Attributes): Point xref to section
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@ -5748,11 +5748,15 @@
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if (TARGET_XOP)
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{
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rtx t3 = gen_reg_rtx (V2DImode);
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emit_insn (gen_sse2_pshufd_1 (t1, op1, GEN_INT (0), GEN_INT (2),
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GEN_INT (1), GEN_INT (3)));
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emit_insn (gen_sse2_pshufd_1 (t2, op2, GEN_INT (0), GEN_INT (2),
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GEN_INT (1), GEN_INT (3)));
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emit_insn (gen_xop_mulv2div2di3_high (operands[0], t1, t2));
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emit_move_insn (t3, CONST0_RTX (V2DImode));
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emit_insn (gen_xop_pmacsdqh (operands[0], t1, t2, t3));
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DONE;
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}
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@ -5777,11 +5781,15 @@
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if (TARGET_XOP)
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{
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rtx t3 = gen_reg_rtx (V2DImode);
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emit_insn (gen_sse2_pshufd_1 (t1, op1, GEN_INT (0), GEN_INT (2),
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GEN_INT (1), GEN_INT (3)));
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emit_insn (gen_sse2_pshufd_1 (t2, op2, GEN_INT (0), GEN_INT (2),
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GEN_INT (1), GEN_INT (3)));
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emit_insn (gen_xop_mulv2div2di3_low (operands[0], t1, t2));
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emit_move_insn (t3, CONST0_RTX (V2DImode));
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emit_insn (gen_xop_pmacsdql (operands[0], t1, t2, t3));
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DONE;
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}
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@ -9792,11 +9800,11 @@
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(sign_extend:V2DI
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(vec_select:V2SI
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(match_operand:V4SI 1 "nonimmediate_operand" "%x")
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(parallel [(const_int 1) (const_int 3)])))
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(parallel [(const_int 0) (const_int 2)])))
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(sign_extend:V2DI
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(vec_select:V2SI
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(match_operand:V4SI 2 "nonimmediate_operand" "xm")
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(parallel [(const_int 1) (const_int 3)]))))
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(parallel [(const_int 0) (const_int 2)]))))
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(match_operand:V2DI 3 "nonimmediate_operand" "x")))]
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"TARGET_XOP"
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"vp<macs>dql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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@ -9810,93 +9818,17 @@
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(sign_extend:V2DI
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(vec_select:V2SI
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(match_operand:V4SI 1 "nonimmediate_operand" "%x")
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(parallel [(const_int 0) (const_int 2)])))
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(parallel [(const_int 1) (const_int 3)])))
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(sign_extend:V2DI
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(vec_select:V2SI
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(match_operand:V4SI 2 "nonimmediate_operand" "xm")
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(parallel [(const_int 0) (const_int 2)]))))
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(parallel [(const_int 1) (const_int 3)]))))
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(match_operand:V2DI 3 "nonimmediate_operand" "x")))]
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"TARGET_XOP"
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"vp<macs>dqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
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[(set_attr "type" "ssemuladd")
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(set_attr "mode" "TI")])
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;; We don't have a straight 32-bit parallel multiply and extend on XOP, so
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;; fake it with a multiply/add. In general, we expect the define_split to
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;; occur before register allocation, so we have to handle the corner case where
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;; the target is the same as operands 1/2
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(define_insn_and_split "xop_mulv2div2di3_low"
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[(set (match_operand:V2DI 0 "register_operand" "=&x")
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(mult:V2DI
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(sign_extend:V2DI
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(vec_select:V2SI
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(match_operand:V4SI 1 "register_operand" "%x")
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(parallel [(const_int 1) (const_int 3)])))
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(sign_extend:V2DI
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(vec_select:V2SI
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(match_operand:V4SI 2 "nonimmediate_operand" "xm")
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(parallel [(const_int 1) (const_int 3)])))))]
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"TARGET_XOP"
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"#"
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"&& reload_completed"
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[(set (match_dup 0)
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(match_dup 3))
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(set (match_dup 0)
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(plus:V2DI
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(mult:V2DI
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(sign_extend:V2DI
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(vec_select:V2SI
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(match_dup 1)
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(parallel [(const_int 1) (const_int 3)])))
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(sign_extend:V2DI
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(vec_select:V2SI
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(match_dup 2)
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(parallel [(const_int 1) (const_int 3)]))))
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(match_dup 0)))]
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{
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operands[3] = CONST0_RTX (V2DImode);
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}
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[(set_attr "type" "ssemul")
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(set_attr "mode" "TI")])
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;; We don't have a straight 32-bit parallel multiply and extend on XOP, so
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;; fake it with a multiply/add. In general, we expect the define_split to
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;; occur before register allocation, so we have to handle the corner case where
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;; the target is the same as either operands[1] or operands[2]
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(define_insn_and_split "xop_mulv2div2di3_high"
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[(set (match_operand:V2DI 0 "register_operand" "=&x")
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(mult:V2DI
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(sign_extend:V2DI
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(vec_select:V2SI
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(match_operand:V4SI 1 "register_operand" "%x")
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(parallel [(const_int 0) (const_int 2)])))
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(sign_extend:V2DI
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(vec_select:V2SI
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(match_operand:V4SI 2 "nonimmediate_operand" "xm")
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(parallel [(const_int 0) (const_int 2)])))))]
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"TARGET_XOP"
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"#"
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"&& reload_completed"
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[(set (match_dup 0)
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(match_dup 3))
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(set (match_dup 0)
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(plus:V2DI
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(mult:V2DI
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(sign_extend:V2DI
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(vec_select:V2SI
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(match_dup 1)
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(parallel [(const_int 0) (const_int 2)])))
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(sign_extend:V2DI
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(vec_select:V2SI
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(match_dup 2)
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(parallel [(const_int 0) (const_int 2)]))))
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(match_dup 0)))]
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{
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operands[3] = CONST0_RTX (V2DImode);
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}
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[(set_attr "type" "ssemul")
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(set_attr "mode" "TI")])
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;; XOP parallel integer multiply/add instructions for the intrinisics
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(define_insn "xop_p<macs>wd"
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[(set (match_operand:V4SI 0 "register_operand" "=x")
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@ -1,3 +1,9 @@
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2012-05-09 Uros Bizjak <ubizjak@gmail.com>
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PR target/52908
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* gcc.target/i386/xop-imul32widen-vector.c: Update scan-assembler
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directive to Scan for vpmuldq, not vpmacsdql.
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2012-05-09 Michael Matz <matz@suse.de>
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PR tree-optimization/53185
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@ -32,5 +32,5 @@ int main ()
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exit (0);
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}
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/* { dg-final { scan-assembler "vpmacsdql" } } */
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/* { dg-final { scan-assembler "vpmuldq" } } */
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/* { dg-final { scan-assembler "vpmacsdqh" } } */
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