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s390.c: (s390_const_double_ok_for_constraint_p): New function.
2005-05-10 Adrian Straetling <straetling@de.ibm.com>
* config/s390/s390.c: (s390_const_double_ok_for_constraint_p): New
function.
(legitimate_reload_constant_p): Add check for const double zero.
* config/s390/s390.md: Add comment for constraint letter 'G'.
("*movdf_64", "*movdf_31", "movsf"): Add constraint and proper
attributes for new case.
* config/s390/s390.h: (CONST_DOUBLE_OK_FOR_CONSTRAINT_P): Define it as
s390_const_double_ok_for_constraint_p.
* config/s390/s390-protos.h (s390_const_double_ok_for_constraint_p):
Add prototype.
From-SVN: r99541
This commit is contained in:
Adrian Straetling
Ulrich Weigand
parent
31117a5ce2
commit
d096725d26
@ -1,3 +1,16 @@
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2005-05-10 Adrian Straetling <straetling@de.ibm.com>
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* config/s390/s390.c: (s390_const_double_ok_for_constraint_p): New
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function.
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(legitimate_reload_constant_p): Add check for const double zero.
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* config/s390/s390.md: Add comment for constraint letter 'G'.
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("*movdf_64", "*movdf_31", "movsf"): Add constraint and proper
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attributes for new case.
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* config/s390/s390.h: (CONST_DOUBLE_OK_FOR_CONSTRAINT_P): Define it as
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s390_const_double_ok_for_constraint_p.
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* config/s390/s390-protos.h (s390_const_double_ok_for_constraint_p):
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Add prototype.
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2005-05-10 Kazu Hirata <kazu@cs.umass.edu>
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PR tree-optimization/21170
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@ -33,6 +33,7 @@ extern void s390_conditional_register_usage (void);
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#ifdef RTX_CODE
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extern int s390_extra_constraint_str (rtx, int, const char *);
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extern int s390_const_ok_for_constraint_p (HOST_WIDE_INT, int, const char *);
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extern int s390_const_double_ok_for_constraint_p (rtx, int, const char *);
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extern int s390_single_part (rtx, enum machine_mode, enum machine_mode, int);
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extern unsigned HOST_WIDE_INT s390_extract_part (rtx, enum machine_mode, int);
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extern bool s390_split_ok_p (rtx, rtx, enum machine_mode, int);
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@ -1679,6 +1679,27 @@ s390_extra_constraint_str (rtx op, int c, const char * str)
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/* Return true if VALUE matches the constraint STR. */
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int
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s390_const_double_ok_for_constraint_p (rtx value,
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int c,
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const char * str)
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{
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gcc_assert (c == str[0]);
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switch (str[0])
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{
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case 'G':
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/* The floating point zero constant. */
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return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
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&& value == CONST0_RTX (GET_MODE (value)));
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default:
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return 0;
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}
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}
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/* Return true if VALUE matches the constraint STR. */
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int
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s390_const_ok_for_constraint_p (HOST_WIDE_INT value,
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int c,
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@ -2190,6 +2211,11 @@ legitimate_reload_constant_p (rtx op)
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&& larl_operand (op, VOIDmode))
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return true;
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/* Accept lzXX operands. */
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if (GET_CODE (op) == CONST_DOUBLE
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&& CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
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return true;
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/* Everything else cannot be handled without reload. */
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return false;
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}
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@ -485,7 +485,8 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
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#define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
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s390_const_ok_for_constraint_p ((VALUE), (C), (STR))
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#define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE, C, STR) 1
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#define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
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s390_const_double_ok_for_constraint_p ((VALUE), (C), (STR))
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#define EXTRA_CONSTRAINT_STR(OP, C, STR) \
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s390_extra_constraint_str ((OP), (C), (STR))
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@ -29,6 +29,7 @@
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;; d -- Any register from 0 to 15.
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;; f -- Floating point registers.
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;; t -- Access registers 36 and 37.
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;; G -- Const double zero operand
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;; I -- An 8-bit constant (0..255).
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;; J -- A 12-bit constant (0..4095).
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;; K -- A 16-bit constant (-32768..32767).
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@ -1364,10 +1365,11 @@
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"")
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(define_insn "*movdf_64"
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[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
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(match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
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[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q")
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(match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))]
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"TARGET_64BIT"
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"@
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lzdr\t%0
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ldr\t%0,%1
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ld\t%0,%1
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ldy\t%0,%1
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@ -1377,14 +1379,15 @@
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lg\t%0,%1
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stg\t%1,%0
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#"
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[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
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(set_attr "type" "floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
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[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
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(set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")])
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(define_insn "*movdf_31"
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[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
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(match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
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[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,Q,d,o,Q")
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(match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,d,dKm,d,Q"))]
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"!TARGET_64BIT"
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"@
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lzdr\t%0
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ldr\t%0,%1
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ld\t%0,%1
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ldy\t%0,%1
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@ -1395,8 +1398,8 @@
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#
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#
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#"
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[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
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(set_attr "type" "floaddf,floaddf,floaddf,fstoredf,fstoredf,lm,stm,*,*,*")])
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[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
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(set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lm,stm,*,*,*")])
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(define_split
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[(set (match_operand:DF 0 "nonimmediate_operand" "")
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@ -1457,10 +1460,11 @@
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;
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(define_insn "movsf"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
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(match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
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[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q")
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(match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))]
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""
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"@
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lzer\t%0
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ler\t%0,%1
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le\t%0,%1
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ley\t%0,%1
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@ -1472,8 +1476,8 @@
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st\t%1,%0
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sty\t%1,%0
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#"
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[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
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(set_attr "type" "floadsf,floadsf,floadsf,fstoresf,fstoresf,
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[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
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(set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf,
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lr,load,load,store,store,*")])
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;
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