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i386.md (nonmemory_operand): New mode attribute.
* config/i386/i386.md (nonmemory_operand): New mode attribute. (push memory peephole2): Macroize peepholes using SWI mode iterator. (move immediate to memory peephole2): Macroize peepholes using SWI124 mode iterator. (non-pairable NOT peephole2): Macroize peepholes using SWI124 mode iterator. (simple lea add peephole2): Macroize peepholes using SWI48 mode iterator. (simple lea mult peephole2): Ditto. (imul by 3,5,9 to lea peephole2): Ditto. (mov $-1, reg peephole2): Macroize peepholes using SWI248 mode iterator. (imul $32bit_imm,mem,reg peephole2): Ditto. (imul $8/16bit_imm,regmem,reg peephole2): Ditto. From-SVN: r163766
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
999a9cc54f
commit
cfc20f00b6
@ -1,3 +1,20 @@
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2010-09-02 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (nonmemory_operand): New mode attribute.
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(push memory peephole2): Macroize peepholes using SWI mode iterator.
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(move immediate to memory peephole2): Macroize peepholes using
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SWI124 mode iterator.
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(non-pairable NOT peephole2): Macroize peepholes using SWI124
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mode iterator.
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(simple lea add peephole2): Macroize peepholes using SWI48
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mode iterator.
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(simple lea mult peephole2): Ditto.
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(imul by 3,5,9 to lea peephole2): Ditto.
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(mov $-1, reg peephole2): Macroize peepholes using SWI248
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mode iterator.
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(imul $32bit_imm,mem,reg peephole2): Ditto.
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(imul $8/16bit_imm,regmem,reg peephole2): Ditto.
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2010-09-02 Ian Bolton <ian.bolton@arm.com>
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* tree-ssa-loop-prefetch.c: Fix comment at head of file.
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@ -858,6 +858,13 @@
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(SI "immediate_operand")
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(DI "x86_64_immediate_operand")])
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;; Nonmemory operand predicate for integer modes.
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(define_mode_attr nonmemory_operand
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[(QI "nonmemory_operand")
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(HI "nonmemory_operand")
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(SI "nonmemory_operand")
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(DI "x86_64_nonmemory_operand")])
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;; Operand predicate for shifts.
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(define_mode_attr shift_operand
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[(QI "nonimmediate_operand")
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@ -1659,8 +1666,7 @@
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"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
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&& !x86_64_immediate_operand (operands[1], DImode)"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (match_dup 2))]
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"")
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(set (match_dup 0) (match_dup 2))])
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;; We need to define this as both peepholer and splitter for case
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;; peephole2 pass is not run.
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@ -2027,8 +2033,7 @@
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"TARGET_64BIT && !symbolic_operand (operands[1], DImode)
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&& !x86_64_immediate_operand (operands[1], DImode)"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (match_dup 2))]
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"")
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(set (match_dup 0) (match_dup 2))])
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;; We need to define this as both peepholer and splitter for case
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;; peephole2 pass is not run.
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@ -4598,8 +4603,7 @@
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"TARGET_SHORTEN_X87_SSE
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&& !(TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ())
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&& peep2_reg_dead_p (2, operands[0])"
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[(set (match_dup 2) (fix:SSEMODEI24 (match_dup 1)))]
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"")
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[(set (match_dup 2) (fix:SSEMODEI24 (match_dup 1)))])
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;; Avoid vector decoded forms of the instruction.
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(define_peephole2
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@ -4608,8 +4612,7 @@
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(fix:SSEMODEI24 (match_operand:DF 1 "memory_operand" "")))]
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"TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
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"")
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(set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))])
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(define_peephole2
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[(match_scratch:SF 2 "x")
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@ -4617,8 +4620,7 @@
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(fix:SSEMODEI24 (match_operand:SF 1 "memory_operand" "")))]
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"TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
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"")
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(set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))])
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(define_insn_and_split "fix_trunc<mode>_fisttp_i387_1"
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[(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
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@ -15829,8 +15831,7 @@
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(use (match_dup 3))
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(clobber (match_dup 0))
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(clobber (match_dup 1))
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(clobber (match_dup 2))])]
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"")
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(clobber (match_dup 2))])])
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;; ...and this one handles cmpstrn*_1.
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(define_peephole2
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@ -15865,10 +15866,7 @@
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(use (reg:CC FLAGS_REG))
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(clobber (match_dup 0))
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(clobber (match_dup 1))
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(clobber (match_dup 2))])]
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"")
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(clobber (match_dup 2))])])
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;; Conditional move instructions.
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@ -16184,11 +16182,13 @@
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;; The % modifier is not operational anymore in peephole2's, so we have to
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;; swap the operands manually in the case of addition and multiplication.
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"if (COMMUTATIVE_ARITH_P (operands[2]))
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operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), GET_MODE (operands[2]),
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operands[0], operands[1]);
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operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]),
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GET_MODE (operands[2]),
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operands[0], operands[1]);
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else
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operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]), GET_MODE (operands[2]),
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operands[1], operands[0]);")
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operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[2]),
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GET_MODE (operands[2]),
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operands[1], operands[0]);")
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;; Conditional addition patterns
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(define_expand "add<mode>cc"
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@ -16198,7 +16198,6 @@
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(match_operand:SWI 3 "const_int_operand" "")]
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""
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"if (ix86_expand_int_addcc (operands)) DONE; else FAIL;")
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;; Misc patterns (?)
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@ -16529,26 +16528,15 @@
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;; Don't push memory operands
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(define_peephole2
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[(set (match_operand:SI 0 "push_operand" "")
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(match_operand:SI 1 "memory_operand" ""))
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(match_scratch:SI 2 "r")]
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[(set (match_operand:SWI 0 "push_operand" "")
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(match_operand:SWI 1 "memory_operand" ""))
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(match_scratch:SWI 2 "<r>")]
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"optimize_insn_for_speed_p () && !TARGET_PUSH_MEMORY
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&& !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (match_dup 2))]
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"")
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(set (match_dup 0) (match_dup 2))])
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(define_peephole2
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[(set (match_operand:DI 0 "push_operand" "")
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(match_operand:DI 1 "memory_operand" ""))
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(match_scratch:DI 2 "r")]
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"optimize_insn_for_speed_p () && !TARGET_PUSH_MEMORY
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&& !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (match_dup 2))]
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"")
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;; We need to handle SFmode only, because DFmode and XFmode is split to
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;; We need to handle SFmode only, because DFmode and XFmode are split to
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;; SImode pushes.
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(define_peephole2
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[(set (match_operand:SF 0 "push_operand" "")
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@ -16557,51 +16545,16 @@
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"optimize_insn_for_speed_p () && !TARGET_PUSH_MEMORY
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&& !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (match_dup 2))]
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"")
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(define_peephole2
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[(set (match_operand:HI 0 "push_operand" "")
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(match_operand:HI 1 "memory_operand" ""))
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(match_scratch:HI 2 "r")]
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"optimize_insn_for_speed_p () && !TARGET_PUSH_MEMORY
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&& !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (match_dup 2))]
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"")
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(define_peephole2
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[(set (match_operand:QI 0 "push_operand" "")
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(match_operand:QI 1 "memory_operand" ""))
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(match_scratch:QI 2 "q")]
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"optimize_insn_for_speed_p () && !TARGET_PUSH_MEMORY
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&& !RTX_FRAME_RELATED_P (peep2_next_insn (0))"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (match_dup 2))]
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"")
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(set (match_dup 0) (match_dup 2))])
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;; Don't move an immediate directly to memory when the instruction
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;; gets too big.
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(define_peephole2
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[(match_scratch:SI 1 "r")
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(set (match_operand:SI 0 "memory_operand" "")
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[(match_scratch:SWI124 1 "<r>")
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(set (match_operand:SWI124 0 "memory_operand" "")
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(const_int 0))]
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"optimize_insn_for_speed_p ()
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&& ! TARGET_USE_MOV0
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&& TARGET_SPLIT_LONG_MOVES
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&& get_attr_length (insn) >= ix86_cur_cost ()->large_insn
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 1) (const_int 0))
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(clobber (reg:CC FLAGS_REG))])
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(set (match_dup 0) (match_dup 1))]
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"")
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(define_peephole2
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[(match_scratch:HI 1 "r")
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(set (match_operand:HI 0 "memory_operand" "")
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(const_int 0))]
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"optimize_insn_for_speed_p ()
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&& ! TARGET_USE_MOV0
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&& !TARGET_USE_MOV0
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&& TARGET_SPLIT_LONG_MOVES
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&& get_attr_length (insn) >= ix86_cur_cost ()->large_insn
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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@ -16611,51 +16564,14 @@
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"operands[2] = gen_lowpart (SImode, operands[1]);")
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(define_peephole2
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[(match_scratch:QI 1 "q")
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(set (match_operand:QI 0 "memory_operand" "")
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(const_int 0))]
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"optimize_insn_for_speed_p ()
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&& ! TARGET_USE_MOV0
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&& TARGET_SPLIT_LONG_MOVES
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&& get_attr_length (insn) >= ix86_cur_cost ()->large_insn
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 2) (const_int 0))
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(clobber (reg:CC FLAGS_REG))])
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(set (match_dup 0) (match_dup 1))]
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"operands[2] = gen_lowpart (SImode, operands[1]);")
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(define_peephole2
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[(match_scratch:SI 2 "r")
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(set (match_operand:SI 0 "memory_operand" "")
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(match_operand:SI 1 "immediate_operand" ""))]
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[(match_scratch:SWI124 2 "<r>")
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(set (match_operand:SWI124 0 "memory_operand" "")
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(match_operand:SWI124 1 "immediate_operand" ""))]
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"optimize_insn_for_speed_p ()
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&& TARGET_SPLIT_LONG_MOVES
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&& get_attr_length (insn) >= ix86_cur_cost ()->large_insn"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (match_dup 2))]
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"")
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(define_peephole2
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[(match_scratch:HI 2 "r")
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(set (match_operand:HI 0 "memory_operand" "")
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(match_operand:HI 1 "immediate_operand" ""))]
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"optimize_insn_for_speed_p ()
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&& TARGET_SPLIT_LONG_MOVES
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&& get_attr_length (insn) >= ix86_cur_cost ()->large_insn"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (match_dup 2))]
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"")
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(define_peephole2
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[(match_scratch:QI 2 "q")
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(set (match_operand:QI 0 "memory_operand" "")
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(match_operand:QI 1 "immediate_operand" ""))]
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"optimize_insn_for_speed_p ()
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&& TARGET_SPLIT_LONG_MOVES
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&& get_attr_length (insn) >= ix86_cur_cost ()->large_insn"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (match_dup 2))]
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"")
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(set (match_dup 0) (match_dup 2))])
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;; Don't compare memory with zero, load and use a test instead.
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(define_peephole2
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@ -16666,8 +16582,7 @@
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(match_scratch:SI 3 "r")]
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"optimize_insn_for_speed_p () && ix86_match_ccmode (insn, CCNOmode)"
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[(set (match_dup 3) (match_dup 2))
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(set (match_dup 0) (match_op_dup 1 [(match_dup 3) (const_int 0)]))]
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"")
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(set (match_dup 0) (match_op_dup 1 [(match_dup 3) (const_int 0)]))])
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;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
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;; Don't split NOTs with a displacement operand, because resulting XOR
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@ -16681,46 +16596,18 @@
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;; lifetime information then.
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(define_peephole2
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[(set (match_operand:SI 0 "nonimmediate_operand" "")
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(not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
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[(set (match_operand:SWI124 0 "nonimmediate_operand" "")
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(not:SWI124 (match_operand:SWI124 1 "nonimmediate_operand" "")))]
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"optimize_insn_for_speed_p ()
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&& ((TARGET_NOT_UNPAIRABLE
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&& (!MEM_P (operands[0])
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|| !memory_displacement_operand (operands[0], SImode)))
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|| (TARGET_NOT_VECTORMODE && long_memory_operand (operands[0], SImode)))
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&& (!MEM_P (operands[0])
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|| !memory_displacement_operand (operands[0], <MODE>mode)))
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|| (TARGET_NOT_VECTORMODE
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&& long_memory_operand (operands[0], <MODE>mode)))
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0)
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(xor:SI (match_dup 1) (const_int -1)))
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(clobber (reg:CC FLAGS_REG))])]
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"")
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(define_peephole2
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[(set (match_operand:HI 0 "nonimmediate_operand" "")
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(not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
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"optimize_insn_for_speed_p ()
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&& ((TARGET_NOT_UNPAIRABLE
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&& (!MEM_P (operands[0])
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|| !memory_displacement_operand (operands[0], HImode)))
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|| (TARGET_NOT_VECTORMODE && long_memory_operand (operands[0], HImode)))
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0)
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(xor:HI (match_dup 1) (const_int -1)))
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(clobber (reg:CC FLAGS_REG))])]
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"")
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(define_peephole2
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[(set (match_operand:QI 0 "nonimmediate_operand" "")
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(not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
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"optimize_insn_for_speed_p ()
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&& ((TARGET_NOT_UNPAIRABLE
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&& (!MEM_P (operands[0])
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|| !memory_displacement_operand (operands[0], QImode)))
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|| (TARGET_NOT_VECTORMODE && long_memory_operand (operands[0], QImode)))
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&& peep2_regno_dead_p (0, FLAGS_REG)"
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[(parallel [(set (match_dup 0)
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(xor:QI (match_dup 1) (const_int -1)))
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(clobber (reg:CC FLAGS_REG))])]
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"")
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(xor:SWI124 (match_dup 1) (const_int -1)))
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(clobber (reg:CC FLAGS_REG))])])
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;; Non pairable "test imm, reg" instructions can be translated to
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;; "and imm, reg" if reg dies. The "and" form is also shorter (one
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@ -16744,8 +16631,7 @@
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(match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3))
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(const_int 0)]))
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(set (match_dup 2)
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(and:SI (match_dup 2) (match_dup 3)))])]
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"")
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(and:SI (match_dup 2) (match_dup 3)))])])
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;; We don't need to handle HImode case, because it will be promoted to SImode
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;; on ! TARGET_PARTIAL_REG_STALL
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@ -16765,8 +16651,7 @@
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(match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3))
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(const_int 0)]))
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(set (match_dup 2)
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(and:QI (match_dup 2) (match_dup 3)))])]
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"")
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(and:QI (match_dup 2) (match_dup 3)))])])
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(define_peephole2
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[(set (match_operand 0 "flags_reg_operand" "")
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@ -16799,8 +16684,7 @@
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(match_dup 2)
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(const_int 8)
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(const_int 8))
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||||
(match_dup 3)))])]
|
||||
"")
|
||||
(match_dup 3)))])])
|
||||
|
||||
;; Don't do logical operations with memory inputs.
|
||||
(define_peephole2
|
||||
@ -16814,8 +16698,7 @@
|
||||
[(set (match_dup 2) (match_dup 1))
|
||||
(parallel [(set (match_dup 0)
|
||||
(match_op_dup 3 [(match_dup 0) (match_dup 2)]))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"")
|
||||
(clobber (reg:CC FLAGS_REG))])])
|
||||
|
||||
(define_peephole2
|
||||
[(match_scratch:SI 2 "r")
|
||||
@ -16828,8 +16711,7 @@
|
||||
[(set (match_dup 2) (match_dup 1))
|
||||
(parallel [(set (match_dup 0)
|
||||
(match_op_dup 3 [(match_dup 2) (match_dup 0)]))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"")
|
||||
(clobber (reg:CC FLAGS_REG))])])
|
||||
|
||||
;; Prefer Load+RegOp to Mov+MemOp. Watch out for cases when the memory address
|
||||
;; refers to the destination of the load!
|
||||
@ -16863,8 +16745,7 @@
|
||||
|| (SSE_REG_P (operands[0]) && SSE_REG_P (operands[1])))"
|
||||
[(set (match_dup 0) (match_dup 2))
|
||||
(set (match_dup 0)
|
||||
(match_op_dup 3 [(match_dup 0) (match_dup 1)]))]
|
||||
"")
|
||||
(match_op_dup 3 [(match_dup 0) (match_dup 1)]))])
|
||||
|
||||
; Don't do logical operations with memory outputs
|
||||
;
|
||||
@ -16886,8 +16767,7 @@
|
||||
(parallel [(set (match_dup 2)
|
||||
(match_op_dup 3 [(match_dup 2) (match_dup 1)]))
|
||||
(clobber (reg:CC FLAGS_REG))])
|
||||
(set (match_dup 0) (match_dup 2))]
|
||||
"")
|
||||
(set (match_dup 0) (match_dup 2))])
|
||||
|
||||
(define_peephole2
|
||||
[(match_scratch:SI 2 "r")
|
||||
@ -16903,8 +16783,7 @@
|
||||
(parallel [(set (match_dup 2)
|
||||
(match_op_dup 3 [(match_dup 1) (match_dup 2)]))
|
||||
(clobber (reg:CC FLAGS_REG))])
|
||||
(set (match_dup 0) (match_dup 2))]
|
||||
"")
|
||||
(set (match_dup 0) (match_dup 2))])
|
||||
|
||||
;; Attempt to always use XOR for zeroing registers.
|
||||
(define_peephole2
|
||||
@ -16916,9 +16795,7 @@
|
||||
&& peep2_regno_dead_p (0, FLAGS_REG)"
|
||||
[(parallel [(set (match_dup 0) (const_int 0))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
{
|
||||
operands[0] = gen_lowpart (word_mode, operands[0]);
|
||||
})
|
||||
"operands[0] = gen_lowpart (word_mode, operands[0]);")
|
||||
|
||||
(define_peephole2
|
||||
[(set (strict_low_part (match_operand 0 "register_operand" ""))
|
||||
@ -16930,66 +16807,48 @@
|
||||
[(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
|
||||
(clobber (reg:CC FLAGS_REG))])])
|
||||
|
||||
;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
|
||||
;; For HI, SI and DI modes, or $-1,reg is smaller than mov $-1,reg.
|
||||
(define_peephole2
|
||||
[(set (match_operand 0 "register_operand" "")
|
||||
[(set (match_operand:SWI248 0 "register_operand" "")
|
||||
(const_int -1))]
|
||||
"(GET_MODE (operands[0]) == HImode
|
||||
|| GET_MODE (operands[0]) == SImode
|
||||
|| (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
|
||||
&& (optimize_insn_for_size_p () || TARGET_MOVE_M1_VIA_OR)
|
||||
"(optimize_insn_for_size_p () || TARGET_MOVE_M1_VIA_OR)
|
||||
&& peep2_regno_dead_p (0, FLAGS_REG)"
|
||||
[(parallel [(set (match_dup 0) (const_int -1))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"operands[0] = gen_lowpart (GET_MODE (operands[0]) == DImode ? DImode : SImode,
|
||||
operands[0]);")
|
||||
{
|
||||
if (GET_MODE_SIZE (<MODE>mode) < GET_MODE_SIZE (SImode))
|
||||
operands[0] = gen_lowpart (SImode, operands[0]);
|
||||
})
|
||||
|
||||
;; Attempt to convert simple lea to add/shift.
|
||||
;; These can be created by move expanders.
|
||||
|
||||
;; Attempt to convert simple leas to adds. These can be created by
|
||||
;; move expanders.
|
||||
(define_peephole2
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(plus:SI (match_dup 0)
|
||||
(match_operand:SI 1 "nonmemory_operand" "")))]
|
||||
[(set (match_operand:SWI48 0 "register_operand" "")
|
||||
(plus:SWI48 (match_dup 0)
|
||||
(match_operand:SWI48 1 "<nonmemory_operand>" "")))]
|
||||
"peep2_regno_dead_p (0, FLAGS_REG)"
|
||||
[(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"")
|
||||
[(parallel [(set (match_dup 0) (plus:SWI48 (match_dup 0) (match_dup 1)))
|
||||
(clobber (reg:CC FLAGS_REG))])])
|
||||
|
||||
(define_peephole2
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(subreg:SI (plus:DI (match_operand:DI 1 "register_operand" "")
|
||||
(match_operand:DI 2 "nonmemory_operand" "")) 0))]
|
||||
"peep2_regno_dead_p (0, FLAGS_REG) && REGNO (operands[0]) == REGNO (operands[1])"
|
||||
"TARGET_64BIT
|
||||
&& peep2_regno_dead_p (0, FLAGS_REG)
|
||||
&& REGNO (operands[0]) == REGNO (operands[1])"
|
||||
[(parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"operands[2] = gen_lowpart (SImode, operands[2]);")
|
||||
|
||||
(define_peephole2
|
||||
[(set (match_operand:DI 0 "register_operand" "")
|
||||
(plus:DI (match_dup 0)
|
||||
(match_operand:DI 1 "x86_64_general_operand" "")))]
|
||||
"peep2_regno_dead_p (0, FLAGS_REG)"
|
||||
[(parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"")
|
||||
|
||||
(define_peephole2
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(mult:SI (match_dup 0)
|
||||
(match_operand:SI 1 "const_int_operand" "")))]
|
||||
[(set (match_operand:SWI48 0 "register_operand" "")
|
||||
(mult:SWI48 (match_dup 0)
|
||||
(match_operand:SWI48 1 "const_int_operand" "")))]
|
||||
"exact_log2 (INTVAL (operands[1])) >= 0
|
||||
&& peep2_regno_dead_p (0, FLAGS_REG)"
|
||||
[(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
|
||||
|
||||
(define_peephole2
|
||||
[(set (match_operand:DI 0 "register_operand" "")
|
||||
(mult:DI (match_dup 0)
|
||||
(match_operand:DI 1 "const_int_operand" "")))]
|
||||
"exact_log2 (INTVAL (operands[1])) >= 0
|
||||
&& peep2_regno_dead_p (0, FLAGS_REG)"
|
||||
[(parallel [(set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))
|
||||
[(parallel [(set (match_dup 0) (ashift:SWI48 (match_dup 0) (match_dup 2)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));")
|
||||
|
||||
@ -16997,7 +16856,8 @@
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(subreg:SI (mult:DI (match_operand:DI 1 "register_operand" "")
|
||||
(match_operand:DI 2 "const_int_operand" "")) 0))]
|
||||
"exact_log2 (INTVAL (operands[2])) >= 0
|
||||
"TARGET_64BIT
|
||||
&& exact_log2 (INTVAL (operands[2])) >= 0
|
||||
&& REGNO (operands[0]) == REGNO (operands[1])
|
||||
&& peep2_regno_dead_p (0, FLAGS_REG)"
|
||||
[(parallel [(set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))
|
||||
@ -17171,23 +17031,23 @@
|
||||
;; Convert imul by three, five and nine into lea
|
||||
(define_peephole2
|
||||
[(parallel
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(mult:SI (match_operand:SI 1 "register_operand" "")
|
||||
(match_operand:SI 2 "const_int_operand" "")))
|
||||
[(set (match_operand:SWI48 0 "register_operand" "")
|
||||
(mult:SWI48 (match_operand:SWI48 1 "register_operand" "")
|
||||
(match_operand:SWI48 2 "const_int_operand" "")))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"INTVAL (operands[2]) == 3
|
||||
|| INTVAL (operands[2]) == 5
|
||||
|| INTVAL (operands[2]) == 9"
|
||||
[(set (match_dup 0)
|
||||
(plus:SI (mult:SI (match_dup 1) (match_dup 2))
|
||||
(match_dup 1)))]
|
||||
(plus:SWI48 (mult:SWI48 (match_dup 1) (match_dup 2))
|
||||
(match_dup 1)))]
|
||||
"operands[2] = GEN_INT (INTVAL (operands[2]) - 1);")
|
||||
|
||||
(define_peephole2
|
||||
[(parallel
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
|
||||
(match_operand:SI 2 "const_int_operand" "")))
|
||||
[(set (match_operand:SWI48 0 "register_operand" "")
|
||||
(mult:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "")
|
||||
(match_operand:SWI48 2 "const_int_operand" "")))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"optimize_insn_for_speed_p ()
|
||||
&& (INTVAL (operands[2]) == 3
|
||||
@ -17195,69 +17055,23 @@
|
||||
|| INTVAL (operands[2]) == 9)"
|
||||
[(set (match_dup 0) (match_dup 1))
|
||||
(set (match_dup 0)
|
||||
(plus:SI (mult:SI (match_dup 0) (match_dup 2))
|
||||
(match_dup 0)))]
|
||||
(plus:SWI48 (mult:SWI48 (match_dup 0) (match_dup 2))
|
||||
(match_dup 0)))]
|
||||
"operands[2] = GEN_INT (INTVAL (operands[2]) - 1);")
|
||||
|
||||
(define_peephole2
|
||||
[(parallel
|
||||
[(set (match_operand:DI 0 "register_operand" "")
|
||||
(mult:DI (match_operand:DI 1 "register_operand" "")
|
||||
(match_operand:DI 2 "const_int_operand" "")))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"TARGET_64BIT
|
||||
&& (INTVAL (operands[2]) == 3
|
||||
|| INTVAL (operands[2]) == 5
|
||||
|| INTVAL (operands[2]) == 9)"
|
||||
[(set (match_dup 0)
|
||||
(plus:DI (mult:DI (match_dup 1) (match_dup 2))
|
||||
(match_dup 1)))]
|
||||
"operands[2] = GEN_INT (INTVAL (operands[2]) - 1);")
|
||||
|
||||
(define_peephole2
|
||||
[(parallel
|
||||
[(set (match_operand:DI 0 "register_operand" "")
|
||||
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
|
||||
(match_operand:DI 2 "const_int_operand" "")))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"TARGET_64BIT
|
||||
&& optimize_insn_for_speed_p ()
|
||||
&& (INTVAL (operands[2]) == 3
|
||||
|| INTVAL (operands[2]) == 5
|
||||
|| INTVAL (operands[2]) == 9)"
|
||||
[(set (match_dup 0) (match_dup 1))
|
||||
(set (match_dup 0)
|
||||
(plus:DI (mult:DI (match_dup 0) (match_dup 2))
|
||||
(match_dup 0)))]
|
||||
"operands[2] = GEN_INT (INTVAL (operands[2]) - 1);")
|
||||
|
||||
;; Imul $32bit_imm, mem, reg is vector decoded, while
|
||||
;; imul $32bit_imm, mem, reg is vector decoded, while
|
||||
;; imul $32bit_imm, reg, reg is direct decoded.
|
||||
(define_peephole2
|
||||
[(match_scratch:DI 3 "r")
|
||||
(parallel [(set (match_operand:DI 0 "register_operand" "")
|
||||
(mult:DI (match_operand:DI 1 "memory_operand" "")
|
||||
(match_operand:DI 2 "immediate_operand" "")))
|
||||
[(match_scratch:SWI48 3 "r")
|
||||
(parallel [(set (match_operand:SWI48 0 "register_operand" "")
|
||||
(mult:SWI48 (match_operand:SWI48 1 "memory_operand" "")
|
||||
(match_operand:SWI48 2 "immediate_operand" "")))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p ()
|
||||
&& !satisfies_constraint_K (operands[2])"
|
||||
[(set (match_dup 3) (match_dup 1))
|
||||
(parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"")
|
||||
|
||||
(define_peephole2
|
||||
[(match_scratch:SI 3 "r")
|
||||
(parallel [(set (match_operand:SI 0 "register_operand" "")
|
||||
(mult:SI (match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "immediate_operand" "")))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p ()
|
||||
&& !satisfies_constraint_K (operands[2])"
|
||||
[(set (match_dup 3) (match_dup 1))
|
||||
(parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"")
|
||||
(parallel [(set (match_dup 0) (mult:SWI48 (match_dup 3) (match_dup 2)))
|
||||
(clobber (reg:CC FLAGS_REG))])])
|
||||
|
||||
(define_peephole2
|
||||
[(match_scratch:SI 3 "r")
|
||||
@ -17266,59 +17080,29 @@
|
||||
(mult:SI (match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "immediate_operand" ""))))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p ()
|
||||
"TARGET_64BIT
|
||||
&& TARGET_SLOW_IMUL_IMM32_MEM && optimize_insn_for_speed_p ()
|
||||
&& !satisfies_constraint_K (operands[2])"
|
||||
[(set (match_dup 3) (match_dup 1))
|
||||
(parallel [(set (match_dup 0)
|
||||
(zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
"")
|
||||
(clobber (reg:CC FLAGS_REG))])])
|
||||
|
||||
;; imul $8/16bit_imm, regmem, reg is vector decoded.
|
||||
;; Convert it into imul reg, reg
|
||||
;; It would be better to force assembler to encode instruction using long
|
||||
;; immediate, but there is apparently no way to do so.
|
||||
(define_peephole2
|
||||
[(parallel [(set (match_operand:DI 0 "register_operand" "")
|
||||
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "")
|
||||
(match_operand:DI 2 "const_int_operand" "")))
|
||||
[(parallel [(set (match_operand:SWI248 0 "register_operand" "")
|
||||
(mult:SWI248
|
||||
(match_operand:SWI248 1 "nonimmediate_operand" "")
|
||||
(match_operand:SWI248 2 "const_int_operand" "")))
|
||||
(clobber (reg:CC FLAGS_REG))])
|
||||
(match_scratch:DI 3 "r")]
|
||||
(match_scratch:SWI248 3 "r")]
|
||||
"TARGET_SLOW_IMUL_IMM8 && optimize_insn_for_speed_p ()
|
||||
&& satisfies_constraint_K (operands[2])"
|
||||
[(set (match_dup 3) (match_dup 2))
|
||||
(parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
{
|
||||
if (!rtx_equal_p (operands[0], operands[1]))
|
||||
emit_move_insn (operands[0], operands[1]);
|
||||
})
|
||||
|
||||
(define_peephole2
|
||||
[(parallel [(set (match_operand:SI 0 "register_operand" "")
|
||||
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
|
||||
(match_operand:SI 2 "const_int_operand" "")))
|
||||
(clobber (reg:CC FLAGS_REG))])
|
||||
(match_scratch:SI 3 "r")]
|
||||
"TARGET_SLOW_IMUL_IMM8 && optimize_insn_for_speed_p ()
|
||||
&& satisfies_constraint_K (operands[2])"
|
||||
[(set (match_dup 3) (match_dup 2))
|
||||
(parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
{
|
||||
if (!rtx_equal_p (operands[0], operands[1]))
|
||||
emit_move_insn (operands[0], operands[1]);
|
||||
})
|
||||
|
||||
(define_peephole2
|
||||
[(parallel [(set (match_operand:HI 0 "register_operand" "")
|
||||
(mult:HI (match_operand:HI 1 "nonimmediate_operand" "")
|
||||
(match_operand:HI 2 "immediate_operand" "")))
|
||||
(clobber (reg:CC FLAGS_REG))])
|
||||
(match_scratch:HI 3 "r")]
|
||||
"TARGET_SLOW_IMUL_IMM8 && optimize_insn_for_speed_p ()"
|
||||
[(set (match_dup 3) (match_dup 2))
|
||||
(parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
|
||||
(parallel [(set (match_dup 0) (mult:SWI248 (match_dup 0) (match_dup 3)))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
{
|
||||
if (!rtx_equal_p (operands[0], operands[1]))
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user